Power gating a portion of a cache memory
First Claim
Patent Images
1. A processor comprising:
- a plurality of tiles, each tile including a core and a tile cache hierarchy, each core including a decoder to decode instructions, at least one execution unit to execute the decoded instructions, and a retirement unit to retire executed instructions, the tile cache hierarchy including a first level cache and a second level cache, wherein each of the first level cache and the second level cache is physically private to the tile; and
a controller coupled to the plurality of tiles, the controller including a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a first tile and to cause the second level cache of the first tile to be independently power gated when a miss rate of the first level cache is less than a first threshold, based at least in part on the utilization information.
0 Assignments
0 Petitions
Accused Products
Abstract
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
-
Citations
17 Claims
-
1. A processor comprising:
-
a plurality of tiles, each tile including a core and a tile cache hierarchy, each core including a decoder to decode instructions, at least one execution unit to execute the decoded instructions, and a retirement unit to retire executed instructions, the tile cache hierarchy including a first level cache and a second level cache, wherein each of the first level cache and the second level cache is physically private to the tile; and a controller coupled to the plurality of tiles, the controller including a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a first tile and to cause the second level cache of the first tile to be independently power gated when a miss rate of the first level cache is less than a first threshold, based at least in part on the utilization information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method comprising:
-
determining an estimated idle duration for a core of a multicore processor, the core associated with a private cache hierarchy including a first level cache, a mid-level cache (MLC) and a last level cache (LLC); determining a time value for a break even condition, wherein the break even condition is a minimum amount of time for the LLC to be in a low power state; receiving performance metric information from the private cache hierarchy; comparing the performance metric information to a threshold value; and power gating the LLC when the estimated idle duration is greater than the time value, while at least one other core of the multicore processor associated with another private cache hierarchy remains in an active state. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. An apparatus comprising:
a multicore processor having a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first cache, a second cache and a third cache, wherein each of the first cache, the second cache and the third cache are private to the tile, and a cache power control logic is to receive performance metric information regarding the tile cache hierarchy of a first tile of the plurality of tiles and to cause the third cache of the first tile to be power gated when a miss rate of the second cache is less than a first threshold based at least in part on the performance metric information, while the core, the first cache and the second cache of the first tile remain in an active state. - View Dependent Claims (16, 17)
Specification