Memory access during memory calibration

• US 9,176,903 B2
• Filed: 11/07/2011
• Issued: 11/03/2015
• Est. Priority Date: 11/09/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian, Ware, Frederick A.
• Primary Examiner(s): SCHNEE, HAL W
• Application Number:
  US13/883,542
• Publication Number:
  US 20130227183A1
• Time in Patent Office: 1,457 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors

Abstract

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Claims

1. A method of controlling first and second ranks of memory devices, coupled to a memory controller, via data buses that include at least a first data bus and a second data bus both of which are coupled to a first memory device in the first memory rank and a second memory device in the second memory rank, the method comprising:

performing a calibration operation that pertains to transmission of data between the first memory device and the memory controller via the first data bus; and

while performing the calibration operation, transferring data, via the second data bus, between the second memory device and the memory controller.

2. The method of claim 1, wherein the data is transferred between the memory controller and a storage location of a selected sub-bank, wherein the selected sub-bank is a sub-bank of a plurality of sub-banks of the second memory device.

3. The method of claim 2, further comprising transmitting a control signal to the second memory device, the control signal specifying accessing, via the second data bus, the storage location of the selected sub-bank.

4. The method of claim 1, further comprising transmitting a control signal to the second memory device, the control signal specifying settings of a routing circuit in the second memory device, the routing circuit permitting access to a sub-bank of a plurality of sub-banks of the second memory device via the second data bus.

5. The method of claim 4 wherein the control signal specifies at least one of a first mode of operation and a second mode of operation, wherein:

in the first mode of operation, the routing circuit is configured to provide data access to the sub-bank via the second data bus while the calibration operation is being performed on the first data bus; and

in the second mode of operation, the routing circuit is configured to provide data access to the sub-bank via the first data bus while no calibration operation is being performed on the first data bus.

6. The method of claim 1, further comprising

performing another calibration operation that pertains to transmission of data between the second memory device and the memory controller via the first data bus;

and

while performing the another calibration operation, transferring data via the second data bus between the first memory device and the memory controller.

7. The method of claim 1, further comprising transmitting a command to perform a core maintenance operation, wherein the calibration operation is performed while at least one of the first memory device and the second memory device performs the core maintenance operation.

8. The method of claim 7, wherein the core maintenance operation is one of a refresh operation, an erase operation, a program operation, and an anneal operation.

9. A memory controller that controls the operation of a plurality of ranks of memory devices including at least a first memory device in a first memory rank and a second memory device in a second memory rank, each memory device coupled to both a first data bus and second data bus, the memory controller comprising:

a circuit to generate a first command that specifies a calibration operation and a second command that specifies a memory access operation; and

an interface to transmit the first command to the first memory device, and the second command to the second memory device, such that the memory access operation is performed by the second memory device while the calibration operation is performed by the first memory device.

10. The memory controller of claim 9, wherein the second command specifies the second memory device to transfer data between the memory controller and a storage location of a selected sub-bank, wherein the selected sub-bank is a sub-bank of a plurality of sub-banks of the second memory device.

11. The memory controller of claim 10, wherein the circuit generates a control signal, the control signal specifying accessing, via the second data bus, the storage location of the selected sub-bank.

12. The memory controller of claim 9, wherein the circuit generates a control signal specifying settings of a routing circuit in the second memory device, the routing circuit permitting access to a sub-bank of a plurality of sub-banks of the second memory device during the memory access operation.

13. The memory controller of claim 12 wherein the control signal specifies at least one of a first mode of operation and a second mode of operation, wherein:

in the first mode of operation, the routing circuit is configured to provide data access to the sub-bank via the second data bus while the calibration operation is being performed on the first data bus; and

in the second mode of operation, the routing circuit is configured to provide data access to the sub-bank via the first data bus while no calibration operation is being performed on the first data bus.

14. The memory controller of claim 9, wherein the circuit generates a third command that specifies a core maintenance operation by at least one of the first memory device and the second memory device, the calibration operation being performed by the first memory device while at least one of the first memory device and the second memory device performs the core maintenance operation.

15. The memory controller of claim 14, wherein the core maintenance operation is one of a refresh operation, an erase operation, a program operation, and an anneal operation.

16. A method of controlling a memory system including a plurality of ranks of memory devices including at least a first memory device in a first memory rank and a second memory device in a second memory rank, each memory device coupled to both a first data bus and second data bus, the method comprising:

transmitting a first command to the first memory device, wherein the first command specifies a calibration operation; and

transmitting a second command to the second memory device, wherein the second command specifies a memory access operation, such that the memory access operation is performed by the second memory device while the calibration operation is performed by the first memory device.

17. The method of claim 16, wherein the second command specifies the second memory device to transfer data between the memory controller and a storage location of a selected sub-bank, wherein the selected sub-bank is a sub-bank of a plurality of sub-banks of the second memory device.

18. The method of claim 17, further comprising transmitting a control signal, the control signal specifying accessing, via the second data bus, the storage location of the selected sub-bank.

19. The method of claim 16, further comprising transmitting a control signal specifying settings of a routing circuit in the second memory device, the routing circuit permitting access to a sub-bank of a plurality of sub-banks of the second memory device during the memory access operation.

20. The method of claim 19 wherein the control signal specifies at least one of a first mode of operation and a second mode of operation, wherein:

in the first mode of operation, the routing circuit is configured to provide data access to the sub-bank via the second data bus while the calibration operation is being performed on the first data bus; and

in the second mode of operation, the routing circuit is configured to provide data access to the sub-bank via the first data bus while no calibration operation is being performed on the first data bus.

21. The method of claim 16, further comprising transmitting a third command to at least one of the first memory device and the second memory device that specifies a core maintenance operation, and wherein the calibration operation is performed by the first memory device while the at least one of the first memory device and the second memory device performs the core maintenance operation.

22. The method of claim 21, wherein the core maintenance operation is one of a refresh operation, an erase operation, a program operation, and an anneal operation.