Smart bridge for memory core

• US 9,177,609 B2
• Filed: 09/28/2011
• Issued: 11/03/2015
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: D'Abreu, Manuel Antonio, Skala, Stephen, Pantelakis, Dimitris, Nair, Radhakrishnan, Pancholi, Deepak
• Primary Examiner(s): Yang, Han
• Application Number:
  US13/247,635
• Publication Number:
  US 20130003480A1
• Time in Patent Office: 1,497 Days
• Field of Search: 365/189.03, 365/189.04, 365/189.18, 365/219, 365/174, 714/766, 714/763, 714/772
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.

Claims

1. An apparatus comprising:

a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first memory die includes circuitry associated with operation of the multiple memory cells;

a second memory die comprising a second memory core; and

a periphery die coupled to the first memory die and to the second memory die, wherein

the periphery die comprises;

periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core;

a first error correction coding (ECC) engine;

a second ECC engine; and

control circuitry configured to perform a first ECC operation at the first ECC engine substantially concurrently with performing a second ECC operation at the second ECC engine, and

wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core.

2. The apparatus of claim 1, wherein the periphery die is configured to perform the first memory operation substantially concurrently with performing the second memory operation.

3. The apparatus of claim 1, wherein the periphery die is configured to receive data from the memory controller, wherein the first memory operation includes storing a first portion of the data to the first 3D memory core, and wherein the second memory operation includes storing a second portion of the data to the second memory core.

4. The apparatus of claim 1, wherein the periphery die is configured to receive a request from the memory controller to retrieve stored data, wherein the first memory operation includes reading a first portion of the stored data from the first 3D memory core, and wherein the second memory operation includes reading a second portion of the stored data from the second memory core.

5. The apparatus of claim 1, wherein the periphery die is configured to receive a request from the memory controller to erase stored data, wherein the first memory operation includes erasing a first portion of the stored data from the first 3D memory core, and wherein the second memory operation includes erasing a second portion of the stored data from the second memory core.

6. The apparatus of claim 1, wherein the first memory operation includes a write operation of first data and the second memory operation includes a read operation of second data, and wherein the periphery die is configured to perform the write operation substantially concurrently with performing the read operation.

7. The apparatus of claim 1, wherein the first ECC operation includes encoding first data at the first ECC engine and wherein the second ECC operation includes encoding second data at the second ECC engine.

8. The apparatus of claim 7, wherein the first data is a first portion of received data from the memory controller and wherein the second data is a second portion of the received data from the memory controller.

9. The apparatus of claim 7, wherein the periphery die is configured to store a first codeword generated by the first ECC operation to the first 3D memory core and to store a second codeword generated by the second ECC operation to the second memory core.

10. The apparatus of claim 1, wherein the first ECC operation includes decoding first data at the first ECC engine and wherein the second ECC operation includes decoding second data at the second ECC engine.

11. The apparatus of claim 10, wherein the first data corresponds to a first portion of data requested by the memory controller and wherein the second data corresponds to a second portion of the data requested by the memory controller.

12. The apparatus of claim 10, wherein the periphery die is configured to retrieve a first representation of a first codeword from the first 3D memory core to be decoded by the first ECC operation and to retrieve a second representation of a second codeword from the second memory core to be decoded by the second ECC operation.

27. The apparatus of claim 1, wherein the substrate is a silicon substrate.

28. The apparatus of claim 1, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the first 3D memory core and to be responsive to a read instruction to read data from the memory cells of the first 3D memory core.

13. A method comprising:

receiving a request at a periphery die, the request received from a memory controller coupled to the periphery die; and

in response to the request;

initiating a first memory operation at a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory core includes circuitry associated with operation of the multiple memory cells;

initiating a second memory operation at a second memory die comprising a second memory core; and

performing a first error correction coding (ECC) operation at a first ECC engine substantially concurrently with performing a second ECC operation at a second ECC engine,

wherein the periphery die comprises the first ECC engine, the second ECC engine, periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core.

14. The method of claim 13, wherein the periphery die is configured to perform the first memory operation substantially concurrently with performing the second memory operation.

15. The method of claim 13, wherein the request is a request to store data, wherein the first memory operation includes storing a first portion of the data to the first 3D memory core and wherein the second memory operation includes storing a second portion of the data to the second memory core.

16. The method of claim 13, wherein the request is a request to retrieve stored data, wherein the first memory operation includes reading a first portion of the stored data from the first 3D memory core and wherein the second memory operation includes reading a second portion of the stored data from the second memory core.

17. The method of claim 13, wherein the request is a request to erase stored data, wherein the first memory operation includes erasing a first portion of the stored data at the first 3D memory core and wherein the second memory operation includes erasing a second portion of the stored data at the second memory core.

18. The method of claim 13, wherein the first memory operation includes a write operation of first data, wherein the second memory operation includes a read operation of second data, and wherein the write operation is performed substantially concurrently with performing the read operation.

19. The method of claim 13, wherein the first ECC operation includes encoding first data at the first ECC engine and wherein the second ECC operation includes encoding second data at the second ECC engine.

20. The method of claim 19, wherein the first data is a first portion of received data from the memory controller and wherein the second data is a second portion of the received data from the memory controller.

21. The method of claim 19, wherein the first memory operation includes storing a first codeword generated by the first ECC operation to the first 3D memory core and wherein the second memory operation includes storing a second codeword generated by the second ECC operation to the second memory core.

22. The method of claim 13, wherein the first ECC operation includes decoding first data at the first ECC engine and wherein the second ECC operation includes decoding second data at the second ECC engine.

23. The method of claim 22, wherein the first data corresponds to a first portion of data requested by the memory controller and wherein the second data corresponds to a second portion of the data requested by the memory controller.

24. The method of claim 22, wherein the first memory operation includes retrieving a first representation of a first codeword from the first 3D memory core to be decoded by the first ECC operation and wherein the second memory operation includes retrieving a second representation of a second codeword from the second memory core to be decoded by the second ECC operation.

29. The method of claim 13, wherein the substrate is a silicon substrate.

30. The method of claim 13, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the first 3D memory core and to be responsive to a read instruction to read data from the memory cells of the first 3D memory core.

25. An apparatus comprising:

a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory core includes circuitry associated with operation of the multiple memory cells;

a second memory die comprising a second memory core; and

a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core, and wherein the periphery die further comprises control circuitry configured to perform a first error correction coding (ECC) operation at a first ECC engine substantially concurrently with performing a second ECC operation at a second ECC engine.

26. The apparatus of claim 25, wherein the first ECC operation includes encoding first data at the first ECC engine and wherein the second ECC operation includes encoding second data at the second ECC engine.

31. The apparatus of claim 25, wherein the substrate is a silicon substrate.

32. The apparatus of claim 25, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the first 3D memory core and to be responsive to a read instruction to read data from the memory cells of the first 3D memory core.