Smart bridge for memory core
First Claim
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1. An apparatus comprising:
- a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first memory die includes circuitry associated with operation of the multiple memory cells;
a second memory die comprising a second memory core; and
a periphery die coupled to the first memory die and to the second memory die, whereinthe periphery die comprises;
periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core;
a first error correction coding (ECC) engine;
a second ECC engine; and
control circuitry configured to perform a first ECC operation at the first ECC engine substantially concurrently with performing a second ECC operation at the second ECC engine, andwherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core.
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Abstract
An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.
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Citations
32 Claims
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1. An apparatus comprising:
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a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first memory die includes circuitry associated with operation of the multiple memory cells; a second memory die comprising a second memory core; and a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die comprises; periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core; a first error correction coding (ECC) engine; a second ECC engine; and control circuitry configured to perform a first ECC operation at the first ECC engine substantially concurrently with performing a second ECC operation at the second ECC engine, and wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28)
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13. A method comprising:
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receiving a request at a periphery die, the request received from a memory controller coupled to the periphery die; and in response to the request; initiating a first memory operation at a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory core includes circuitry associated with operation of the multiple memory cells; initiating a second memory operation at a second memory die comprising a second memory core; and performing a first error correction coding (ECC) operation at a first ECC engine substantially concurrently with performing a second ECC operation at a second ECC engine, wherein the periphery die comprises the first ECC engine, the second ECC engine, periphery circuitry corresponding to the first 3D memory core and periphery circuitry corresponding to the second memory core. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 29, 30)
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25. An apparatus comprising:
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a first memory die comprising a first three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate, wherein the first 3D memory core includes circuitry associated with operation of the multiple memory cells; a second memory die comprising a second memory core; and a periphery die coupled to the first memory die and to the second memory die, wherein the periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first 3D memory core and a second memory operation at the second memory core, and wherein the periphery die further comprises control circuitry configured to perform a first error correction coding (ECC) operation at a first ECC engine substantially concurrently with performing a second ECC operation at a second ECC engine. - View Dependent Claims (26, 31, 32)
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Specification