Smart bridge for memory core

• US 9,177,610 B2
• Filed: 04/07/2014
• Issued: 11/03/2015
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: D'Abreu, Manuel Antonio, Skala, Stephen, Pantelakis, Dimitris, Nair, Radhakrishnan, Pancholi, Deepak
• Primary Examiner(s): Yang, Han
• Application Number:
  US14/246,593
• Publication Number:
  US 20140218997A1
• Time in Patent Office: 575 Days
• Field of Search: 365/189.17, 365/189.18, 365/219, 365/174
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

Claims

1. An apparatus comprising:

a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells; and

a second semiconductor die including;

a memory device interface;

a memory controller interface; and

periphery circuitry associated with the 3D memory;

wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface, and wherein the memory controller interface is configured to be coupled to a memory interface of a memory controller die to enable communication of data and control information between the memory controller die and the 3D memory via the memory device interface and the memory controller interface of the second semiconductor die.

2. The apparatus of claim 1, wherein the periphery circuitry is coupled to the 3D memory via the memory device interface, and wherein the memory device interface includes a differential signaling interface.

3. The apparatus of claim 2, wherein the memory controller die includes a second differential signaling interface.

4. The apparatus of claim 1, wherein the periphery circuitry includes a charge pump configured to generate a voltage to be applied to at least one of a word line, a bit line, or a source line of the 3D memory.

5. The apparatus of claim 1, wherein the periphery circuitry includes a row decoder configured to decode at least a portion of an address and to select a row of the 3D memory based on the portion.

6. The apparatus of claim 1, wherein the substrate is a silicon substrate.

7. The apparatus of claim 1, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

8. A method comprising:

receiving data at a second semiconductor die for storage at a three-dimensional (3D) memory at a first semiconductor die, wherein the second semiconductor die includes a memory device interface, a memory controller interface, and periphery circuitry for the 3D memory; and

sending a control signal from the second semiconductor die to the 3D memory at the first semiconductor die,

wherein the 3D memory includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate and wherein the 3D memory includes circuitry associated with operation of the multiple memory cells,

wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface, and

wherein the memory controller interface is configured to be coupled to a memory interface of a memory controller die to enable communication between the memory controller die and the 3D memory via the memory device interface and the memory controller interface of the second semiconductor die.

9. The method of claim 8, wherein the periphery circuitry includes a different signaling interface.

10. The method of claim 8, wherein the data is received from the memory controller die, and wherein the memory controller die is coupled to the second semiconductor die via the memory controller interface of the second semiconductor die.

11. The method of claim 8, wherein the substrate is a silicon substrate.

12. The method of claim 8, wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.