Apparatuses and methods including memory with top and bottom data lines

• US 9,177,614 B2
• Filed: 07/28/2014
• Issued: 11/03/2015
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/444,589
• Publication Number:
  US 20140334219A1
• Time in Patent Office: 463 Days
• Field of Search: 365/72, 365/185.17, 365/185.18, 365/185.03
• US Class Current: 1/1
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

Claims

1. An apparatus comprising:

a first data line located on a first level of the apparatus;

a second data line located on a second level of the apparatus;

a first memory cell string coupled to the first data line;

a first source coupled to the first memory cell string;

a second memory cell string coupled to the second data line; and

a second source coupled to the second memory cell string, wherein the first and second sources are located in different levels of the apparatus.

2. The apparatus of claim 1, wherein the first source includes a source line located in a level between the first and second level of the apparatus.

3. The apparatus of claim 1, wherein the second source includes a source line located in a level between the first and second levels of the apparatus.

4. The apparatus of claim 1, further comprising an access line shared by a memory cell of the first memory cell string a second memory cell of the second memory cell string.

5. The apparatus of claim 4, further comprising a module configured to concurrently retrieve information from the first and second memory cells during an operation of the apparatus.

6. The apparatus of claim 4, further comprising a module configured to concurrently store information in the first and second memory cells during an operation of the apparatus.

7. The apparatus of claim 1, wherein the apparatus comprises a memory device.

8. The apparatus of claim 1, wherein the apparatus comprises a system including a memory device that includes the first and second date lines, the first and second memory cells, and the first and second sources.

9. An apparatus comprising:

a first set of conductive lines, at least a portion of the first set of conductive lines configured as a first set of data lines;

a second set of conductive lines, at least a portion of the second set of conductive lines configured as a second set of data lines;

memory cells located in different levels of the apparatus and arranged in memory cell strings between the first and second sets of data lines;

a first transistor coupled between a first memory string of the memory cell strings and a first data line of the first set of data lines;

a first select line to provide a signal to control the first transistor;

a second transistor coupled between a second memory cell string of the memory cell strings and a second data line of the second set of data lines;

a second select line to provide a signal to control the second transistor; and

a module configured to concurrently retrieve information from a memory cell of the first memory cell string and a memory cell of the second memory cell string during an operation of the apparatus.

10. The apparatus of claim 9, wherein the module is configured to concurrently store information in the memory cell of the first memory cell string and the memory cell of the second memory cell string during an additional operation of the apparatus.

11. The apparatus of claim 9, further comprising a first source line and a second source line, wherein a first portion of the memory cell strings is coupled to the first source line and the first set of data lines, and a second portion of the memory cell strings is coupled to the second source line and the second set of data lines.

12. The apparatus of claim 11, wherein the first source line is located between the first portion of the memory cell strings and the second set of data lines.

13. The apparatus of claim 12, wherein the second source line is located between the second portion of the memory cell strings and the first set of data lines.

14. The apparatus of claim 9, further including a substrate, wherein one of the first and second sets of data lines is located between the substrate and the memory cells.

15. An apparatus comprising:

memory cells arranged in rows including a first row and a second row, the memory cells including a first memory cell set located in the first row and a second memory cell set located in the second row;

a first set of conductive lines, at least a portion of the first set of conductive lines configured as a first set of data lines;

a second set of conductive lines, at least a portion of the second set of conductive lines configured as a second set of data lines; and

a module configured to concurrently retrieve information from the first and second memory cell sets through the first and second sets of data lines in an operation of the apparatus.

16. The apparatus of claim 15, wherein the module is configured to concurrently store information in the first and second memory cell sets through the first and second sets of data lines in an additional operation of the apparatus.

17. The apparatus of claim 15, further comprising an access line shared by the first and second memory cell sets.

18. The apparatus of claim 15, wherein the memory cells are located in a same level of the apparatus.

19. The apparatus of claim 15, wherein the first and second sets of conductive lines are located in different levels of the apparatus.

20. The apparatus of claim 15, further comprising a source coupled to the first memory cell set and a second source coupled to a second memory cell set, wherein the first and second sources are located in different levels of the apparatus.

21. The apparatus of claim 15, wherein the first and second memory cell sets include an equal quantity of memory cells.