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Dual rail single-ended read data paths for static random access memories

  • US 9,177,635 B1
  • Filed: 04/23/2014
  • Issued: 11/03/2015
  • Est. Priority Date: 04/09/2014
  • Status: Expired due to Fees
First Claim
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1. A Static Random Access Memory (SRAM) device, comprising:

  • a memory cell array;

    a bit line traversing the memory cell array for reading data from memory cells of the memory cell array;

    a read circuit coupled to the bit line for translating data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device, wherein the cell voltage and the peripheral voltage share a common ground, the read circuit comprising;

    a data path circuit configured to toggle a first internal signal between a logical zero of the peripheral voltage and a logical one of the peripheral voltage based on read data on the bit line and a second internal signal, and to toggle a third internal signal between a logical zero of the cell voltage and a logical one of the cell voltage based on an enable signal and the read data on the bit line;

    a level shifter circuit configured to toggle the second internal signal between a logical zero of the peripheral voltage and a logical one of the peripheral voltage based on the third internal signal and a reset signal; and

    an output driver circuit configured to toggle the output of the SRAM device between a logical zero of the peripheral voltage and a logical one of the peripheral voltage based on the first internal signal.

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