Low-voltage fast-write PMOS NVSRAM cell

• US 9,177,644 B2
• Filed: 08/12/2013
• Issued: 11/03/2015
• Est. Priority Date: 08/15/2012
• Status: Expired due to Fees

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Tsao, Hsing-Ya, Lee, Peter Wung
• Primary Examiner(s): Hur, J. H.
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US13/965,031
• Publication Number:
  US 20140050025A1
• Time in Patent Office: 813 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM'"'"'s PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

Claims

1. A 14T PMOS NVSRAM memory cell circuit with low-voltage (LV) fast-write scheme, the 14T PMOS NVSRAM memory cell comprising:

a SRAM cell comprising six LV CMOS transistors operated at a VDD voltage as low as 1.2 V, the six LV CMOS transistors including a pair of LV NMOS transistors sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by another two LV NMOS transistors and two LV PMOS transistors;

a Flash cell comprising a first Flash string of three PMOS transistors and a second Flash string of three PMOS transistors sharing a common N-well region, the first/second Flash string including a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series, the first and the second top Select transistors being gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal, the first and the second bottom Select transistors being gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line for controlling two complementary charge states, the first source terminal and the second source terminal being connected together to a flash source line, and the first drain terminal and the second drain terminal being respectively connected to the first data node and the second data node; and

a pair of Pass transistors respectively disposed to set up a connection in series between the first data node and the first drain terminal and a separate connection in series between the second data node in series and the second drain terminal;

wherein the pair of Pass transistors are commonly gated by a pass-control line to provide two direct routes of writing data of the SRAM cell via a FN-tunneling effect respectively from the first data node and the second data node collectively to the first Flash transistor and the second Flash transistor of the Flash cell in two complementary threshold voltage states without reversing data polarity by setting a negative high voltage VNN ranging from about −

12V to about −

18V to the second word line with the common N-well region being set to the VDD voltage.

2. The 14T PMOS NVSRAM memory cell of claim 1 wherein each of the first and second Flash transistors is a 2-poly floating-gate type HV PMOS transistor including a Poly1 floating gate and a Poly2 control gate over the Poly1 floating gate.

3. The 14T PMOS NVSRAM memory cell of claim 2 wherein each of the first and second top/bottom Select transistors is an 1-poly HV PMOS transistor formed by shorting the Poly2 control gate to the Poly1 floating gate of a 2-poly HV PMOS transistor.

4. The 14T PMOS NVSRAM memory cell of claim 1 wherein each of the first Flash string and the second Flash string comprises an equivalent pull-down resistance of the three PMOS transistors that is lower than the PMOS pull-up resistance of the corresponding SRAM cell for improving data-loading speed from the Flash cell to the SRAM cell during a power-on period to ramp an operation voltage from 0 V to the VDD voltage.

5. The 14T PMOS NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to an Erase operation by setting the second word line to a positive voltage ranging from 12V to 18V to achieve a FN-tunneling effect on each of the two 2-poly floating-gate type HV PMOS transistors along with applying the VDD voltage to the first select-gate control line, grounding the common N-well region, applying 0V to the flash source line, and applying a negative voltage of about −

5V to the second select-gate control line.

6. The 14T PMOS NVSRAM memory cell of claim 5 wherein the pass-control line is set at 0 V for isolating the SRAM cell from each Flash string of the Flash cell during the Erase operation if each of the pair of Pass transistors is a LV NMOS transistor.

7. The 14T PMOS NVSRAM memory cell of claim 5 wherein both the first Flash transistor and the second Flash transistor of the Flash cell are associated with an identical threshold voltage level of no greater than −

2.0 V in less than 10 ms after the Erase operation.

8. The 14T PMOS NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to Program and Program-Inhibit operations by setting the second word line to the VNN voltage to achieve a FN-tunneling effect on each of the first and second Flash transistors along with applying 0 V to the first select-gate control line, the flash source line, and the second select-gate control line, setting the common N-well region to the VDD voltage, and coupling the pass-control line to the VDD voltage plus about 2V margin to open up the connection between the SRAM cell and the Flash cell if each of the pair of Pass transistors is a LV NMOS transistor.

9. The 14T PMOS NVSRAM memory cell of claim 8 wherein any one of the first data node and the second data node of the SRAM cell charged at the VDD voltage corresponding to part of SRAM data is in a conduction state to connect with one of the first Flash transistor and the second transistor enabled by the FN-tunneling effect to change a threshold voltage level from about −

2.0V or smaller to about +2.0 V or greater to be associated with Flash data in less than 10 ms for memory density greater than 200 Mb.

10. The 14T PMOS NVSRAM memory cell of claim 8 wherein any one of the first data node and the second data node of the SRAM cell set at 0 V corresponding to part of SRAM data is in a non-conduction state as the FN-tunneling effect is not enabled, thereby keeping the corresponding one of the first Flash transistor and the second transistor with a threshold voltage level at about −

2.0V or smaller to be associated with Flash data.

11. The 14T PMOS NVSRAM memory cell of claim 8 wherein the Program and Program-Inhibit operations are initiated once power voltage of the SRAM cell drops to below 70% of the VDD voltage during a regular power-down event or an unexpected power-loss event to write data from the SRAM cell to the Flash cell in less than 10 ms.

12. The 14T PMOS NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Read/Write operation therein by setting the first word line to the VDD voltage to allow access of the first data node and the second data node respectively by the first bit line and the second bit line, the Read/Write operation being isolated from the Flash cell by coupling the pass-control signal line to 0V and coupling the first select-gate control line to the VDD voltage.

13. The 14T PMOS NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a data-loading operation from the Flash cell during a power-up period by setting the first word line to 0 V to isolate two LV NMOS transistors from access of the first bit line and the second bit line, coupling both the first select-gate control line and the second select-gate control line to a negative voltage of about −

5 V to open up top/bottom Select transistors with less effective resistance, setting the second word line to 0 V for selectively turning on the first Flash transistor and the second Flash transistor depending on corresponding threshold voltage states for setting respective voltage levels of the first data node and the second data node without changing data polarity.

14. The 14T PMOS NVSRAM memory cell of claim 13 wherein the first data node is set to 0V and the second data node is set to the VDD voltage if correspondingly the first Flash transistor with a threshold voltage of about −

2V or lower is turned on and the second Flash transistor with a threshold voltage of about 2V or greater is turned off by commonly applying VSS to the second word line, applying a negative voltage of about −

5V to both the first select-gate control line and the second select-gate control line, and coupling the pass-control line to the VDD voltage plus about 2V margin if each of the pair of Pass transistors is a LV NMOS transistor.

15. The 14T PMOS NVSRAM memory cell of claim 13 wherein the data-loading operation from the Flash cell into the SRAM cell is initiated following a power-on period whenever a powerline voltage of the SRAM cell is detected to ramp up from 0V to 70% of the VDD voltage of 1.2V to 1.8V or higher, the initiated data loading operation being associated with a control bias condition including setting the VDD voltage to the common N-well region, coupling VDD+2V to the pass-control line, setting a negative voltage of about −

5V to both the first select-gate control line and the second select-gate control line, and keeping 0 V at the first word line and the second word line.

16. The 14T PMOS NVSRAM memory cell of claim 1 wherein each of the pair of LV CMOS transistors is a PMOS transistor being commonly gated by the pass-control signal line set at the VDD voltage for isolating the SRAM cell from each Flash string of the Flash cell during an operation for erasing the Flash cell data and during normal SRAM Read/Write cycle.

17. The 14T PMOS NVSRAM memory cell of claim 1 wherein each of the pair of Pass transistors can be a LV PMOS transistor having an N-well region not shared with the common N-well region of the Flash cell but having a common gate coupled to the pass-control line set at the VDD voltage for isolating the SRAM cell from each Flash string of the Flash cell.

18. A method for operating a PMOS NVSRAM memory cell with a low power-voltage VDD, comprising:

coupling a first word line of both a first data node and a second data node of a SRAM cell through common gates of a first access NMOS transistor and a second access NMOS transistor;

providing a first Flash string of three-PMOS transistors and a second Flash string of three-PMOS transistors respectively connecting in series with the first data node and the second data node, each Flash string including a Flash transistor sandwiched by a top select-gate transistor and a bottom select-gate transistor, both Flash strings being configured to be a Flash cell sharing a common N-well region and a common source line;

coupling a second word line to common gates of the pair of Flash transistors;

coupling a first select-gate control line to common gates of the pair of top select-gate transistor;

coupling a second select-gate control line to common gates of the pair of bottom select-gate transistor;

executing one or more PMOS NVSRAM cell operations including a data-loading operation to write data from the Flash cell into the SRAM cell following a timeline after ramping up of the power voltage VDD from 0V to a desired low voltage VDD level ranging from 1.2 V to 1.8V;

wherein the data-loading operation includes keeping the first word line to 0V, applying −

5V to the first select-gate control line, setting the second word line to 0V, applying −

5V to the second select-gate control line, and setting the common N-well region at the VDD level, thereby the data-loading operation forming a conduction state in a Flash transistor having a channel threshold voltage of −

2.0V in association with the first/second Flash string to set 0V level to the corresponding first/second data node and also forming a non-conduction state in another Flash transistor having a channel threshold voltage of +2.0V in association with the first/second Flash string to set the VDD level to the corresponding first/second data node; and

comprising executing a program/program-inhibit operation in the Flash cell to write data from the Flash cell to the SRAM cell in the timeline associated with a period of less than 10 ms after an occurrence of a regular power-down event or an unexpected power-loss event when the power voltage VDD drops at least below 70% of the desired VDD level, wherein the erase operation includes setting the first word line to 0 V, applying 0 V to the first select-gate control line, setting the second word line to a negative high voltage ranging from −

12 V to −

18 V, applying 0V to the second select-gate control line, and setting the common N-well region to trace the power voltage VDD, thereby the program/program-inhibit operation causing the channel threshold voltage of a Flash transistor in the first/second string to change from −

2.0 V to +2.0 V if the first/second string corresponds to the first/second data node stored at the VDD level and keeping the channel threshold voltage of another Flash transistor in the first/second string at −

2.0 V if the first/second string corresponds to the first/second data node stored at 0V.

19. The method of claim 18 further comprising executing an erase operation in the Flash cell to isolate each Flash string from the SRAM cell and set a Flash channel threshold voltage state of each Flash transistor in each Flash string to a low level of about −

2.0 V or lower in a period less than 10 ms in any time of the timeline after the data loading operation, wherein the erase operation includes keeping the first word line to 0V, applying the VDD level to the first select-gate control line, setting the second word line to a positive high voltage ranging from 12 V to 18 V, applying −

5V to the second select-gate control line, and setting the common N-well region to 0V.

20. The method of claim 18 further comprising executing a read/write operation within the SRAM cell in a period of the timeline by applying the VDD level to the first word line of both a first data node and a second data node of a SRAM cell through common gates of a first access NMOS transistor and a second access NMOS transistor, wherein the SRAM cell is isolated from each Flash string at least by applying the VDD level to the first select-gate control line.