Low-voltage fast-write PMOS NVSRAM cell
First Claim
1. A 14T PMOS NVSRAM memory cell circuit with low-voltage (LV) fast-write scheme, the 14T PMOS NVSRAM memory cell comprising:
- a SRAM cell comprising six LV CMOS transistors operated at a VDD voltage as low as 1.2 V, the six LV CMOS transistors including a pair of LV NMOS transistors sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by another two LV NMOS transistors and two LV PMOS transistors;
a Flash cell comprising a first Flash string of three PMOS transistors and a second Flash string of three PMOS transistors sharing a common N-well region, the first/second Flash string including a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series, the first and the second top Select transistors being gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal, the first and the second bottom Select transistors being gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line for controlling two complementary charge states, the first source terminal and the second source terminal being connected together to a flash source line, and the first drain terminal and the second drain terminal being respectively connected to the first data node and the second data node; and
a pair of Pass transistors respectively disposed to set up a connection in series between the first data node and the first drain terminal and a separate connection in series between the second data node in series and the second drain terminal;
wherein the pair of Pass transistors are commonly gated by a pass-control line to provide two direct routes of writing data of the SRAM cell via a FN-tunneling effect respectively from the first data node and the second data node collectively to the first Flash transistor and the second Flash transistor of the Flash cell in two complementary threshold voltage states without reversing data polarity by setting a negative high voltage VNN ranging from about −
12V to about −
18V to the second word line with the common N-well region being set to the VDD voltage.
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Abstract
This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM'"'"'s PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.
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Citations
20 Claims
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1. A 14T PMOS NVSRAM memory cell circuit with low-voltage (LV) fast-write scheme, the 14T PMOS NVSRAM memory cell comprising:
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a SRAM cell comprising six LV CMOS transistors operated at a VDD voltage as low as 1.2 V, the six LV CMOS transistors including a pair of LV NMOS transistors sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by another two LV NMOS transistors and two LV PMOS transistors; a Flash cell comprising a first Flash string of three PMOS transistors and a second Flash string of three PMOS transistors sharing a common N-well region, the first/second Flash string including a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series, the first and the second top Select transistors being gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal, the first and the second bottom Select transistors being gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line for controlling two complementary charge states, the first source terminal and the second source terminal being connected together to a flash source line, and the first drain terminal and the second drain terminal being respectively connected to the first data node and the second data node; and a pair of Pass transistors respectively disposed to set up a connection in series between the first data node and the first drain terminal and a separate connection in series between the second data node in series and the second drain terminal; wherein the pair of Pass transistors are commonly gated by a pass-control line to provide two direct routes of writing data of the SRAM cell via a FN-tunneling effect respectively from the first data node and the second data node collectively to the first Flash transistor and the second Flash transistor of the Flash cell in two complementary threshold voltage states without reversing data polarity by setting a negative high voltage VNN ranging from about −
12V to about −
18V to the second word line with the common N-well region being set to the VDD voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for operating a PMOS NVSRAM memory cell with a low power-voltage VDD, comprising:
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coupling a first word line of both a first data node and a second data node of a SRAM cell through common gates of a first access NMOS transistor and a second access NMOS transistor; providing a first Flash string of three-PMOS transistors and a second Flash string of three-PMOS transistors respectively connecting in series with the first data node and the second data node, each Flash string including a Flash transistor sandwiched by a top select-gate transistor and a bottom select-gate transistor, both Flash strings being configured to be a Flash cell sharing a common N-well region and a common source line; coupling a second word line to common gates of the pair of Flash transistors; coupling a first select-gate control line to common gates of the pair of top select-gate transistor; coupling a second select-gate control line to common gates of the pair of bottom select-gate transistor; executing one or more PMOS NVSRAM cell operations including a data-loading operation to write data from the Flash cell into the SRAM cell following a timeline after ramping up of the power voltage VDD from 0V to a desired low voltage VDD level ranging from 1.2 V to 1.8V;
wherein the data-loading operation includes keeping the first word line to 0V, applying −
5V to the first select-gate control line, setting the second word line to 0V, applying −
5V to the second select-gate control line, and setting the common N-well region at the VDD level, thereby the data-loading operation forming a conduction state in a Flash transistor having a channel threshold voltage of −
2.0V in association with the first/second Flash string to set 0V level to the corresponding first/second data node and also forming a non-conduction state in another Flash transistor having a channel threshold voltage of +2.0V in association with the first/second Flash string to set the VDD level to the corresponding first/second data node; andcomprising executing a program/program-inhibit operation in the Flash cell to write data from the Flash cell to the SRAM cell in the timeline associated with a period of less than 10 ms after an occurrence of a regular power-down event or an unexpected power-loss event when the power voltage VDD drops at least below 70% of the desired VDD level, wherein the erase operation includes setting the first word line to 0 V, applying 0 V to the first select-gate control line, setting the second word line to a negative high voltage ranging from −
12 V to −
18 V, applying 0V to the second select-gate control line, and setting the common N-well region to trace the power voltage VDD, thereby the program/program-inhibit operation causing the channel threshold voltage of a Flash transistor in the first/second string to change from −
2.0 V to +2.0 V if the first/second string corresponds to the first/second data node stored at the VDD level and keeping the channel threshold voltage of another Flash transistor in the first/second string at −
2.0 V if the first/second string corresponds to the first/second data node stored at 0V. - View Dependent Claims (19, 20)
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Specification