10T NVSRAM cell and cell operations

• US 9,177,645 B2
• Filed: 10/19/2013
• Issued: 11/03/2015
• Est. Priority Date: 10/19/2012
• Status: Expired due to Fees

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Tsao, Hsing-Ya, Lee, Peter Wung
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/058,227
• Publication Number:
  US 20140112072A1
• Time in Patent Office: 745 Days
• Field of Search: 365/154, 365/185.08, 365/185.28, 365/185.29
• US Class Current: 1/1
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ΔVt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM'"'"'s power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ΔVtp≧1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.

Claims

1. A 10T NVSRAM memory cell circuit with a DRAM-like charge-sensing scheme, the 10T NVSRAM memory cell comprising:

a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two invertors, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node; and

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Select transistor and a first/second Flash transistor connected in series, the first and the second Select transistors being gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node, the first and the second Flash transistors being gated commonly by a second word line and respectively associated with a first source terminal and a second source terminal, the first source terminal and the second source terminal being floating;

wherein the second word line is configured to ramp up to a voltage above the VDD level sufficient to couple two different charge levels respectively from the first Flash transistor and the second Flash transistor to the first data node and the second data node, the SRAM cell uses the two cross-coupled inverters to amplify the two different charge levels to one at the VDD level and another one at VSS in a two-step operation;

wherein the first Flash transistor and the second Flash transistor are configured to flexibly increase their channel lengths to make a difference of the two different charge levels coupled to the first data node and the second data node to be substantially larger than any unmatched parasitic capacitance between the first data node and the second data node.

2. The 10T NVSRAM memory cell of claim 1 wherein each of the first Flash transistor and the second Flash transistor is selected from a 2-poly NMOS floating-gate type transistor, a 1-poly SONOS or MONOS charge-trapping type transistor, and a 2-poly PMOS floating-gate type transistor.

3. The 10T NVSRAM memory cell of claim 1 wherein each of the first Select transistor and the second Select transistor is selected from a 1-poly NMOS transistor, a 1-poly PMOS transistor, a 2-poly NMOS floating-gate type with a poly1 layer and poly 2 layer shorted, and a 2-poly PMOS floating-gate type with a poly1 layer and poly 2 layer shorted.

4. The 10T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Read and Write operation by setting the first word line to the VDD level if the SRAM cell is selected or to VSS=0V if the SRAM cell is not selected and applying the VDD level to the first power line and VSS=0V to the second power line, while setting the select-gate control line to VSS=0V to isolated each SRAM cell from each corresponding Flash cell.

5. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to an Erase operation by applying a negative high voltage VNN to the second word line to decrease threshold levels of both the first Flash transistor and the second Flash transistor to a level below −

2.0V under a FN-channel tunneling scheme in less than 10 ms, along with applying the VDD level to the first power line and VSS=0V to the second power line, setting the common P-sub to 0V and setting the select-gate control line to VSS=0V.

6. The 10T NVSRAM memory cell of claim 5 wherein the VNN is ranged from −

15V to −

18V for a 2-poly NMOS or PMOS type of the Flash cell or about −

10V for a 1-poly SONOS or MONOS type of the Flash cell.

7. The 10T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Program operation for defining a flash logic state, the Program operation being associated with an initial setup condition of setting the select-gate control line and the second word line to the VDD level, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

0”

of the SRAM cell with the first data node at VSS=0V and the second data node at the VDD level, the Program operation including ramping up the second word line from the VDD level to a positive high voltage VPP using a FN-channel tunneling scheme to increase threshold level of the first Flash transistor from an initial level <

−

2.0V to a final level ≧

2.0V and to retain threshold level of the second Flash transistor at the initial level, thereby storing the flash logic state “

1”

in the Flash cell.

8. The 10T NVSRAM memory cell of claim 7 wherein the Flash cell is subjected to a Program operation being associated with an initial setup condition of setting the select-gate control line and the second word line to the VDD level, applying the VDD level to the first power line and VSS=0V to the second power line, and loading a logic state “

1”

of the SRAM cell with the first data node at the VDD level and the second data node at VSS, the Program operation including ramping up the second word line from the VDD level to a positive high voltage VPP using a FN-channel tunneling scheme to increase threshold level of the second Flash transistor from the initial level <

−

2.0V to a final level ≧

2.0V and to retain threshold level of the first Flash transistor at the initial level, thereby storing a flash logic state “

0”

in the Flash cell.

9. The 10T NVSRAM memory cell of claim 8 wherein the VPP is ranged from +15V to +18V for a 2-poly NMOS or PMOS type of the Flash cell or about +10V for a 1-poly SONOS or MONOS type of the Flash cell.

10. The 10T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Recall operation for writing a flash logic state stored in the Flash cell back to the first data node and the second data node under a charge-sensing scheme, the flash logic state including at least a state “

1”

defined by a Vt1 threshold level for the first Flash transistor and a Vt0<

Vt1 threshold level for the second Flash transistor or a state “

0”

defined by a Vt0 threshold level for the first Flash transistor and a Vt1>

Vt0 threshold level for the second Flash transistor.

11. The 10T NVSRAM memory cell of claim 10 wherein the Recall operation for writing a flash logic state “

1”

to the SRAM cell comprises a bias condition of pulsing the first word line to the VDD level for setting the first data node, the second data node, the first power line, and the second power line to VSS, setting the select-gate control line to the VDD level plus threshold level of the corresponding Select transistor, ramping the second power line first from VSS to the VDD level and ramping the second word line from VSS to the voltage above the VDD level, and sequentially ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level followed by ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level.

12. The 10T NVSRAM memory cell of claim 11 wherein the voltage above the VDD level comprises a positive value near the Vt1 and still substantially smaller than a Flash programming voltage VPP of about +15V or higher.

13. The 10T NVSRAM memory cell of claim 11 wherein ramping the second word line from VSS to the voltage above the VDD level comprises at least inducing a first capacitance charge at the first Flash transistor and a second capacitance charge at the second Flash transistor, the second capacitance charge being more than the first capacitance charge due to Vt0<

Vt1, and causing the first capacitance charge to pass through the first Select transistor to the first data node and the second capacitance charge to pass through the second Select transistor to the second data node.

14. The 10T NVSRAM memory cell of claim 13 wherein the first capacitance charge is retained in the first data node and the second capacitance charge is retained in the second data node by setting the first power line to VSS and the second power line to the VDD level.

15. The 10T NVSRAM memory cell of claim 13 wherein ramping the first power line from VSS to the VDD level while maintaining the second power line at the VDD level comprises pulling up the second capacitance charge at the second data node to substantially the VDD level in a first SRAM amplification operation.

16. The 10T NVSRAM memory cell of claim 13 wherein ramping the second power line from the VDD level to VSS while maintaining the first power line at the VDD level comprises pulling down the first capacitance charge at the first data node to substantially VSS=0V in a second SRAM amplification operation.