Bad block compensation for solid state storage devices
First Claim
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1. A method for a memory control module, the method comprising:
- identifying an address associated with one or more bad memory cells in a memory page of a solid state storage device;
determining a first address value of a first memory cell in the memory page based at least in part on the address of the one or more bad memory cells of the solid state storage device and a number of correctable bad memory cells in the memory page;
determining a usable size of the memory page based at least in part on the first address value; and
storing the first address value and the determined usable size, wherein the first address value and the determined usable size facilitates utilization of the memory page of the solid state storage device,wherein identifying the address associated with one or more bad memory cells includes identifying addresses associated with uncorrectable bad memory cells in the memory page of the solid state storage device.
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Abstract
Technologies and implementations for reusing bad blocks in a solid state drive are generally disclosed.
11 Citations
26 Claims
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1. A method for a memory control module, the method comprising:
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identifying an address associated with one or more bad memory cells in a memory page of a solid state storage device; determining a first address value of a first memory cell in the memory page based at least in part on the address of the one or more bad memory cells of the solid state storage device and a number of correctable bad memory cells in the memory page; determining a usable size of the memory page based at least in part on the first address value; and storing the first address value and the determined usable size, wherein the first address value and the determined usable size facilitates utilization of the memory page of the solid state storage device, wherein identifying the address associated with one or more bad memory cells includes identifying addresses associated with uncorrectable bad memory cells in the memory page of the solid state storage device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A machine readable non-transitory medium having stored therein instructions that, in response to execution by one or more processors, operatively enable a memory control module to perform or cause to be performed:
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identify an address associated with one or more bad memory cells in a memory page of a solid state storage device; determine a first address value of a first memory cell based at least in part on the one or more bad memory cells of the solid state storage device; determine a forward or backward write direction based on a number of usable memory cells and correctable bad memory cells that precede an uncorrectable bad memory cell in either direction; determine a usable size of the memory page based at least in part on the first address value and the write direction; and store the first address value and the determined usable size. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A system, comprising:
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a solid state storage device; and a memory control module communicatively coupled to the solid state storage device, the memory control module capable of being operatively enabled to perform or cause to be performed; identify an address associated with one or more bad memory cells in a memory page of the solid state storage device; determine a first address value of a first memory cell based at least in part on the one or more bad memory cells of the solid state storage device; and determine a usable size of the memory page based at least in part on the first address value; and store the first address value and the determined usable size, wherein the determined usable size and a direction to write facilitates utilization of the memory page of the solid state storage device, wherein the one or more bad memory cells in the memory page of the solid state storage device are uncorrectable bad memory cells. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification