Method of operating memory device
First Claim
1. A method of operating a memory device having a plurality of memory cells, the method comprising:
- changing a first read voltage, for determining whether data stored in memory cells is a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage within the first range as a first select read voltage; and
changing a second read voltage, for determining whether the data stored in the plurality of memory cells is a third voltage state or a fourth voltage state, to a voltage within a second range which is different from the first range and determining the voltage within the second range as a second select read voltage,wherein the first and second voltage states are different from the third and fourth voltage states, the first voltage state and the second voltage overlap each other, the third voltage state and the fourth voltage state overlap each other, and a difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.
-
Citations
14 Claims
-
1. A method of operating a memory device having a plurality of memory cells, the method comprising:
-
changing a first read voltage, for determining whether data stored in memory cells is a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage within the first range as a first select read voltage; and changing a second read voltage, for determining whether the data stored in the plurality of memory cells is a third voltage state or a fourth voltage state, to a voltage within a second range which is different from the first range and determining the voltage within the second range as a second select read voltage, wherein the first and second voltage states are different from the third and fourth voltage states, the first voltage state and the second voltage overlap each other, the third voltage state and the fourth voltage state overlap each other, and a difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A memory system comprising:
-
a nonvolatile memory device comprising a plurality of memory cells into which data is programmed; and a controller configured to control the nonvolatile memory device, the controller comprising; a microprocessor configured to change a first read voltage, for determining whether the data stored in the memory cells is a first voltage state or a second voltage state, to a voltage within a first range and to determine the voltage within the first range as a first select read voltage, and the microprocessor to change a second read voltage, for determining whether the data stored in the memory cells is a third voltage state or a fourth voltage state, to a voltage within a second range and to determine the voltage within the second range as a second select read voltage; an error correction code (ECC) encoder to create data added with parity bits by performing ECC encoding on data which is to be provided to the nonvolatile memory device; and an ECC decoder to correct error bits of the data added with the parity bits, wherein the nonvolatile memory device comprises; control logic to control operation of the nonvolatile memory device in accordance with received commands; a voltage generator to generate the first and second read voltages, n candidate voltages comprising the first select read voltage, and m candidate voltages comprising the second select read voltage, where n and m are natural numbers; an X decoder to receive the first and second read voltages and the first and second select read voltages generated by the voltage generator and to drive the memory cells using the first and second read voltages and the first and second select read voltages; and a register to store the determined first and second select read voltages. - View Dependent Claims (9, 10)
-
-
11. A memory system comprising:
-
a nonvolatile memory device having a plurality of memory cells into which data is programmed to provide a number of failed programmed memory cells that is less than or equal to a number of failed cells correctable by performing error correction code (ECC) encoding; and a controller configured to change a first read voltage, for determining whether the data stored in the memory cells is a first voltage state or a second voltage state, to a voltage within a first range and to determine the voltage within the first range as a first select read voltage, and the controller configured to change a second read voltage, for determining whether the data stored in the memory cells is a third voltage state or a fourth voltage state, to a voltage within a second range and to determine the voltage within the second range as a second select read voltage, the controller further configured to create data added with parity bits by performing ECC encoding on data which is to be provided to the nonvolatile memory device, and to correct error bits of the data added with the parity bits. - View Dependent Claims (12, 13, 14)
-
Specification