Dynamic regulation of memory array source line

• US 9,177,663 B2
• Filed: 07/18/2013
• Issued: 11/03/2015
• Est. Priority Date: 07/18/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Huynh, Jonathan H., Wang, Sung-En, Pan, Feng
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/945,117
• Publication Number:
  US 20150023100A1
• Time in Patent Office: 838 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation.

Claims

1. A non-volatile memory circuit, comprising:

an array of non-volatile memory cells arranged along a plurality of bit lines connected to a common source line;

a pull down device connected between the common source line and ground, wherein the pull-down device includes a first transistor connected between the common source line and ground and having a gate connected to receive the output of the first op-amp;

a first op-amp having a first input connected to the common source line, a second input connected to receive a first reference level, and an output connected to control the pull down device;

a variable current source connected between a first supply level and the common source line; and

a current comparison circuit connected to the pull down device to perform a comparison of the amount of current flowing through the pull down device to a reference value and having an output connected to control the variable current source based upon the comparison, wherein the current comparison circuit includes;

a current mirror connected between a second supply level and ground, having a first leg connected to ground through a second transistor having a gate connected to receive the output of the first op-amp and a second leg connected to ground through a reference current source, wherein the second supply level is of a higher voltage than the first supply level; and

a second op-amp having a first input connected to receive a second reference level, having a second input connected to a node of the second leg above the reference current source, and having an output that is a voltage level dependent on the value of the second op-amp'"'"'s second input relative to the second reference value and is connected to control the variable current source.

2. The non-volatile memory circuit of claim 1, wherein the variable current source includes a PMOS transistor connected between the first supply level and the common source line having a gate connected to receive the output of the second op-amp.

3. The non-volatile memory circuit of claim 1, wherein the second transistor is sized smaller than the first transistor.

4. The non-volatile memory circuit of claim 1, wherein the current mirror is implemented as a cascode device.

5. A non-volatile memory circuit, comprising:

an array of non-volatile memory cells arranged along a plurality of bit lines connected to a common source line;

a pull down device connected between the common source line and ground, wherein the pull-down device includes a first transistor connected between the common source line and ground and havingagate connected to receive the output of the first op-amp;

a first op-amp having a first input connected to the common source line, a second input connected to receive a first reference level, and an output connected to control the pull down device;

a variable current source connected between a first supply level and the common source line; and

a current cam arison circuit connected to the_pull down device to perform a comparison of the amount of current flowing through the pull down device to a reference value and having an output connected to control the variable current source based upon the comparison, wherein the current comparison circuit includes;

a current mirror connected between a second supply level and ground, having a first leg connected to ground through a second transistor having a gate connected to receive the output of the first op-amp and a second leg connected to ground through a reference current source, wherein the second supply level is of a higher voltage than the first supply level; and

a comparator having a first input connected to receive a second reference level, having a second input connected to a node of the second leg above the reference current source, and having an output that is a plurality of bits dependent on the value of the comparator'"'"'s second input relative to the second reference value and is connected to control the variable current source.

6. The non-volatile memory circuit of claim 5, wherein the variable current source includes a plurality of transistors connected between the first supply level and the common source line having a gate connected to receive the output of the comparator.

7. The non-volatile memory circuit of claim 5, wherein the second transistor is sized smaller than the first transistor.

8. The non-volatile memory circuit of claim 5, wherein the current mirror is implemented as a cascade device.