Tuning capacitance to enhance FET stack voltage withstand

• US 9,177,737 B2
• Filed: 09/16/2013
• Issued: 11/03/2015
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Englekirk, Robert Mark
• Primary Examiner(s): Patel, Reema
• Application Number:
  US14/028,357
• Publication Number:
  US 20140165385A1
• Time in Patent Office: 778 Days
• Field of Search: 257/303, 257/306, 257/386
• US Class Current: 1/1
• CPC Class Codes: H01H 11/00 Apparatus or processes specially adapted for the manufacture of electric switches processes specially adapted for manufacture of rectilinearly movable switches having a plurality of operating members associated with different sets of contacts, e.g. keyboards, H01H13/88
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: Y10T 29/49105 Switch making

Abstract

An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Claims

1. A method of fabricating a stacked RF switch that includes a plurality of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising a step of establishing total effective drain-source capacitance Cds values for each constituent transistor in the stack, wherein the Cds value for each constituent transistor is different and at least two constituent transistors are configured such that their Cds values differ from each other by at least 2%.

2. The method of claim 1 wherein the different Cds between constituent transistors is effective to more uniformly distribute voltage across the constituent transistors, in that a variance of the magnitude of Vds-off as distributed across all the constituent transistors would increase if the differences between Cds values are substantially reduced.

3. The method of claim 1 wherein the at least two constituent transistors are configured such that their Cds values differ from each other by at least 5%.

4. The method of claim 1 wherein the at least two constituent transistors are configured such that their Cds values differ from each other by at least 10%.

5. The method of claim 1, further comprising balancing charge injection for a particular internal node by estimating values of all significant capacitive elements coupled to the particular internal node, estimating a voltage across each such significant capacitive element, and controlling capacitance coupled to the particular node as necessary to approximately zero a sum of all such capacitance values, as multiplied to reflect the corresponding estimated voltage.

6. The method of claim 5, further comprising approximately balancing charge injection for each of a majority of internal nodes of the RF switch stack.

7. The method of claim 6, further comprising approximately balancing charge injection for each internal node of the RF switch stack.

8. The method of claim 1, further comprising coupling a discrete capacitive feature to one or more internal nodes of the stack, where a discrete capacitive feature is a distinct element having an impedance that is predominantly capacitive at a primary frequency of a signal ordinarily switched by the RF switch.

9. A method of fabricating a stacked RF switch that includes a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising coupling a discrete capacitive feature to one or more internal nodes of the stack, where a discrete capacitive feature is a distinct element having an impedance that is predominantly capacitive at a primary frequency of a signal ordinarily switched by the RF switch.

10. The method of claim 9, comprising coupling a plurality of discrete capacitive features to the one or more internal nodes of the stack.

11. The method of claim 9, further comprising balancing voltage distribution by controlling any discrete capacitive features coupled to internal nodes of the stack such that a variance of magnitude in Vds-off, as distributed across all constituent transistors due to a voltage Vsw applied across the RF switch, would increase if all such discrete capacitive features were omitted.

12. The method of claim 9, further comprising determining parasitic drain capacitances coupled to at least one internal node of the series string.

13. The method of claim 12, further comprising determining voltages of internal nodes to which the parasitic drain capacitances are coupled and comparing the determined voltages of the internal nodes to voltages of endnodes of the RF switch.

14. The method of claim 12, wherein determining parasitic drain capacitances comprises analyzing semiconductor device layout geometric parameters.

15. The method of claim 12, further comprising capacitance balancing, wherein capacitance balancing comprises weighting each value of capacitances coupled to a selected internal node of the series string according to a proportion of a switching voltage Vsw across the capacitances coupled to the selected internal node, such that a sum of the weighted capacitances is at or around zero for the selected internal node.

16. The method of claim 15, wherein capacitance balancing is performed for a majority of the internal nodes of the series string or performed for all of the internal nodes of the series string.