Method for yield improvement of TMBS devices

• US 9,177,798 B1
• Filed: 12/17/2014
• Issued: 11/03/2015
• Est. Priority Date: 05/12/2014
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Manufacturing Corporation Limited (GTA Semiconductor Co., Ltd.)
• Original Assignee: Advanced Semiconductor Manufacturing Corporation Limited (GTA Semiconductor Co., Ltd.)
• Inventors: Wang, Xizheng
• Primary Examiner(s): Ho, Tu-Tu
• Application Number:
  US14/573,708
• Publication Number:
  US 20150325675A1
• Time in Patent Office: 321 Days
• Field of Search: 438/237, 438/259, 438/167, 257/288, 257/471, 257/211
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0495 Schottky electrodes
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A method for yield improvement of trench MOS barrier Schottky (TMBS) devices includes: forming a plurality of trenches in a substrate; forming a gate dielectric layer over a surface of the substrate and inner surfaces of the trenches; forming gates in the trenches; forming a first barrier dielectric layer, a second barrier dielectric layer and an intermediate dielectric layer over the trenches; etching the intermediate dielectric layer with the second barrier dielectric layer serving as an etch stop layer to form a window for forming contact holes; etching a portion of the second barrier dielectric layer within the window using the first barrier dielectric layer as an etch stop layer; and etching in the window to remove a portion of the first barrier dielectric layer overlying the gates and a portion of the gate dielectric layer overlying the substrate.

Claims

1. A method for yield improvement of trench MOS barrier Schottky (TMBS) devices, comprising the following steps in the sequence set forth:

providing a substrate with a plurality of trenches formed therein;

forming a gate dielectric layer over a top surface of the substrate and inner surfaces of the plurality of trenches;

forming a plurality of gates in the plurality of trenches, the plurality of gates having top surfaces substantially level with the top surface of the substrate;

forming a first barrier dielectric layer over the top surfaces of the plurality of gates;

sequentially forming a second barrier dielectric layer and an intermediate dielectric layer over the substrate;

etching the intermediate dielectric layer with the second barrier dielectric layer serving as an etch stop layer to form a window for subsequent formation of contact holes;

etching the second barrier dielectric layer within the window using the first barrier dielectric layer as an etch stop layer; and

etching in the window to remove a portion of the first barrier dielectric layer overlying the top surfaces of the plurality of gates and a portion of the gate dielectric layer overlying the top surface of the substrate.

2. The method of claim 1, wherein the formation of the plurality of trenches comprises the steps of:

forming a hard mask layer over the substrate;

forming a patterned photoresist layer over the hard mask layer; and

etching the substrate to form the plurality of trenches with the patterned photoresist layer and the hard mask layer serving as an etching mask.

3. The method of claim 2, further comprising removing the hard mask layer after forming the plurality of trenches.

4. The method of claim 1, wherein forming the gate dielectric layer over the top surface of the substrate and the inner surfaces of the plurality of trenches comprises:

forming a sacrificial oxide layer over the top surface of the substrate and the inner surfaces of the plurality of trenches;

removing the sacrificial oxide layer by using an acid solution; and

forming the gate dielectric layer over the top surface of the substrate and the inner surfaces of the plurality of trenches.

5. The method of claim 4, wherein the sacrificial oxide layer is a silicon oxide layer and the acid solution is hydrofluoric acid.

6. The method of claim 4, wherein the gate dielectric layer is a silicon oxide layer formed by thermal oxidation.

7. The method of claim 1, wherein forming the plurality of gates in the plurality of trenches comprises the steps of:

forming a gate layer over the gate dielectric layer; and

etching the gate layer until a top surface of the etched gate layer is level with the top surface of the substrate.

8. The method of claim 1, wherein the first barrier dielectric layer is a silicon oxide layer formed on the plurality of gates by thermal oxidation.

9. The method of claim 8, wherein the first barrier dielectric layer has a thickness of 500 Å

to 1000 Å

.

10. The method of claim 9, wherein the first barrier dielectric layer is etched by dry etching.

11. The method of claim 1, wherein the second barrier dielectric layer is a silicon oxide layer formed by chemical vapor deposition.

12. The method of claim 11, wherein the second barrier dielectric layer has a thickness of 500 Å

to 700 Å

.

13. The method of claim 12, wherein the second barrier dielectric layer is etched by dry etching.

14. The method of claim 1, wherein the intermediate dielectric layer is a silicon oxide layer formed by chemical vapor deposition.

15. The method of claim 14, wherein the intermediate dielectric layer has a thickness of 3000 Å

to 5000 Å

.

16. The method of claim 15, wherein the intermediate dielectric layer is etched by wet etching.