Power semiconductor device and method therefor

• US 9,177,866 B2
• Filed: 04/14/2015
• Issued: 11/03/2015
• Est. Priority Date: 01/10/2004
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Estivation Properties LLC (Intellectual Ventures LLC)
• Inventors: Davies, Robert Bruce
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US14/685,785
• Publication Number:
  US 20150221558A1
• Time in Patent Office: 203 Days
• Field of Search: 438268-273
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/83193 wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 : specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 : With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Claims

1. A method comprising:

depositing a layer of conductive material over a first surface of a semiconductor material, wherein the semiconductor material comprises a plurality of transistors, and wherein each of the plurality of transistors includes a gate, a drain region, and a source region; and

coupling gates of the plurality of transistors to each other with a mesh structure;

wherein at least a portion of the mesh structure is positioned over the layer of conductive material, and wherein the layer of conductive material is positioned substantially between the mesh structure and the drain regions to thereby reduce gate-to-drain capacitance.

2. The method of claim 1, wherein the layer of conductive material is a shield and comprises polysilicon.

3. The method of claim 1, further comprising coupling a gate contact to the mesh structure.

4. The method of claim 1, further comprising forming openings in the mesh structure, wherein the mesh structure comprises a conductive interconnect material.

5. The method of claim 4, wherein the conductive interconnect material comprises polysilicon.

6. The method of claim 4, further comprising coupling a plurality of source interconnects to each of the source regions and to the layer of conductive material.

7. The method of claim 6, wherein, for each source interconnect, at least a portion of each source interconnect is positioned in one of the openings of the mesh structure and is electrically isolated from the mesh structure.

8. The method of claim 1, wherein the plurality of transistors comprises vertical transistors.

9. A method comprising:

forming a plurality of transistors, wherein each transistor of the plurality of transistors comprises a gate, a drain region, and a source region, and wherein the source regions and at least a portion of the drain regions are in a semiconductor material;

forming a gate interconnect layer to couple the gates of the plurality of transistors to each other; and

forming a mesh-shaped layer of conductive material over a first surface of the semiconductor material substantially between the drain region and the gate interconnect layer to thereby reduce gate-to-drain capacitance.

10. The method of claim 9, wherein the mesh-shaped layer of conductive material is a layer of polysilicon, and wherein the semiconductor material comprises an epitaxial layer.

11. The method of claim 9, further comprising forming openings in the mesh-shaped layer of conductive material, wherein the mesh-shaped layer of conductive material comprises a conductive interconnect material.

12. The method of claim 9, further comprising coupling a metal source interconnect to at least one source region of the plurality of transistors, wherein the mesh-shaped layer of conductive material is electrically coupled to the metal source interconnect.

13. The method of claim 12, further comprising forming a first doped region of a first conductivity type extending from a first surface of the semiconductor material into the semiconductor material, wherein the first doped region is directly connected to the mesh-shaped layer of conductive material at the first surface of the semiconductor material.

14. The method of claim 13, wherein the first region is contiguous around a periphery of the plurality of transistors.

15. A method comprising:

forming a plurality of transistors, wherein each transistor of the plurality of transistors comprises a gate, a drain region, and a source region, and wherein the source regions and at least a portion of the drain regions are formed in a semiconductor material;

coupling the gates of the plurality of transistors to each other with a mesh structure;

forming a layer of conductive material over a first surface of the semiconductor material, wherein at least a portion of the mesh structure is positioned over the layer of conductive material, and wherein the layer of conductive material is positioned substantially between the mesh structure and the drain regions to thereby reduce gate-to-drain capacitance; and

coupling a gate contact to the mesh structure, wherein the gate contact comprises a gate interconnection that is positioned external to the mesh structure and that completely surrounds the mesh structure, and wherein the gate contact is coupled to the gates of the plurality of transistors of the mesh structure via one or more gate pathways.

16. The method of claim 15, further comprising forming a dielectric structure extending from a first surface of the semiconductor material into the semiconductor material, wherein the gate contact is disposed over the dielectric structure.

17. The method of claim 15, wherein the layer of conductive material is a shield and comprises polysilicon.

18. The method of claim 15, further comprising forming openings in the mesh structure, wherein the mesh structure comprises a conductive interconnect material.

19. The method of claim 18, wherein the conductive interconnect material comprises polysilicon.

20. The method of claim 18, further comprising coupling a plurality of source interconnects to each of the source regions and to the layer of conductive material.