Tungsten gates for non-planar transistors

• US 9,177,867 B2
• Filed: 09/30/2011
• Issued: 11/03/2015
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer S., Bergstrom, Daniel B., Chun, Jin-Sung, Chiu, Julia
• Primary Examiner(s): SHOOK, DANIEL P
• Application Number:
  US13/993,330
• Publication Number:
  US 20150041926A1
• Time in Patent Office: 1,495 Days
• Field of Search: 257/412, 438/230
• US Class Current: 1/1
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Claims

1. A transistor gate, comprising:

a pair of gate spacers; and

a gate electrode disposed between the pair of gate spacers, wherein the gate electrode includes;

an NMOS work-function material adjacent at least a portion of the pair of gates spacers and comprising aluminum, titanium, and carbon;

a titanium-containing gate fill barrier adjacent the NMOS work-function material; and

a tungsten-containing gate fill material adjacent the gate fill barrier.

2. The transistor gate of claim 1, wherein the gate electrode is non-planar.

3. The transistor gate of claim 1, wherein the NMOS work-function material comprises between about 20 to 40% by weight aluminum, between about 30 to 50% by weight titanium, and between about 10 to 30% by weight carbon.

4. The transistor gate of claim 1, wherein the NMOS work-function material comprises about 33% by weight aluminum, about 43% by weight titanium, and about 24% by weight carbon.

5. The transistor gate of claim 1, further including a capping dielectric structure disposed adjacent the non-planar gate electrode and between the pair of gate spacers.

6. A method of fabricating a transistor gate, comprising:

forming a pair of gate spacers; and

forming a gate electrode disposed between the pair of gate spacers comprising

conformally depositing an NMOS work-function material adjacent the pair of gates spacers and comprising aluminum, titanium, and carbon;

conformally depositing a titanium-containing gate fill barrier adjacent the NMOS work-function material; and

depositing a tungsten-containing gate fill material adjacent the gate fill barrier.

7. The method of claim 6, wherein conformally depositing the NMOS work-function material comprises conformally depositing the NMOS work-function material having a composition between about 20 to 40% aluminum, between about 30 to 50% titanium, and between about 10 to 30% carbon.

8. The method of claim 7, wherein conformally depositing the NMOS work-function material comprises conformally depositing the NMOS work-function material having a composition of about 33% by weight aluminum, about 43% by weight titanium, and between about 24% by weight carbon.

9. The method of claim 6, further including:

conformally depositing a PMOS work-function material adjacent the pair of gates spacers; and

removing a portion of the PMOS work-function material within areas for fabrication of the NMOS gate electrode prior to depositing the NMOS work-function material.

10. The method of claim 9, wherein conformally depositing the PMOS work-function material comprises conformally depositing a titanium nitride PMOS work-function material.

11. The method of claim 6, further including:

removing a portion of the NMOS work-function material within areas for fabrication of PMOS gate electrodes; and

conformally depositing a PMOS work-function material adjacent the pair of gates spacers and on the NMOS work-function material within areas for fabrication of the NMOS gate electrodes.

12. The method of claim 11, wherein conformally depositing the PMOS work-function material comprises conformally depositing a titanium nitride PMOS work-function material.

13. The method of claim 6, further including:

removing a portion of the NMOS work-function material within areas for fabrication of PMOS gate electrodes; and

conformally depositing a titanium-containing layer as a gate fill barrier adjacent the NMOS work-function material within areas for fabrication of the NMOS gate electrodes and as a PMOS work-function material within areas for fabrication of PMOS gate electrodes.

14. The method of claim 13, wherein conformally depositing a titanium-containing layer comprises conformally depositing a titanium nitride layer.

15. The method of claim 6, further including funning a capping dielectric structure disposed adjacent the non-planar gate electrode and between the pair of gate spacers.

16. The method of claim 15, wherein forming a capping dielectric structure disposed adjacent the non-planar gate electrode and between the pair of gate spacers, comprises:

forming a recess between the gate spacers by removing a portion of the gate electrode; and

depositing a capping dielectric material within the recess.

17. A method of fabricating a non-planar transistor gate, comprising:

forming a sacrificial non-planar transistor gate over a non-planar transistor fin;

depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor tin;

forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;

forming a source/drain region;

removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;

forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;

forming a gate electrode disposed between the pair of gate spacers, comprising

conformally depositing an NMOS work-function material adjacent the pair of gates spacers and comprising aluminum, titanium, and carbon;

conformally depositing a titanium-containing gate fill barrier adjacent the NMOS work-function material; and

depositing a tungsten-containing gate fill material adjacent the gate fill barrier;

removing a portion of the gate electrode to form a recess between the non-planar transistor gate spacers;

forming a capping dielectric structure within the recess;

forming at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and

forming a contact opening through the at least one dielectric material to contact at least a portion of the source/drain region.

18. The method of claim 17, wherein conformally depositing the NMOS work-function material comprises conformally depositing the NMOS work-function material having a composition between about 20 to 0.40% by weight aluminum, between about 30 to 50% by weight titanium, and between about 10 to 30% by weight carbon.

19. The method of claim 17, wherein conformally depositing the NMOS work-function material comprises conformally depositing the NMOS work-function material having a composition of about 33% by weight aluminum, about 43% by weight titanium, and between about 24% by weight carbon.

20. The method of claim 17, further including:

conformally depositing a PMOS work-function material adjacent the pair of gates spacers; and

removing a portion of the PMOS work-function material within areas for fabrication of the NMOS gate electrode prior to depositing the NMOS work-function material.

21. The method of claim 20, wherein conformally depositing the PMOS work-function material comprises conformally depositing a titanium nitride PMOS work-function material.

22. The method of claim 17, further including:

removing a portion of the NMOS work-function material within areas for fabrication of PMOS gate electrodes; and

conformally depositing a PMOS work-function material adjacent the pair of gates spacers and on the NMOS work-function material within areas for fabrication of the NMOS gate electrodes.

23. The method of claim 22, wherein conformally depositing the PMOS work-function material comprises conformally depositing a titanium nitride PMOS work-function material.

24. The method of claim 22, wherein conformally depositing a titanium-containing gate fill barrier comprises conformally depositing a titanium nitride layer.

25. The method of claim 17, further including:

removing a portion of the NMOS work-function material within areas for fabrication of PMOS gate electrodes; and

conformally depositing a titanium-containing layer as a gate fill barrier adjacent the NMOS work-function material within areas for fabrication of the NMOS gate electrodes and as a PMOS work-function material within areas for fabrication of PMOS gate electrodes.