Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method

• US 9,177,884 B2
• Filed: 10/09/2012
• Issued: 11/03/2015
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Schunk, Nikolaus W.
• Primary Examiner(s): Diallo, Mamadou
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US13/647,474
• Publication Number:
  US 20140097536A1
• Time in Patent Office: 1,120 Days
• Field of Search: 257/40, 257/434, 257/738, 257/774, 257/E31.117, 257/E21.135, 438/25
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0384 involving a mechanical process, e.g. planarising the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1204 : Optical Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 31/02325 : the optical elements not being integrated nor being directly associated with the device
• CPC Class Codes: H01L 33/58 : Optical field-shaping elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01S 5/02325 : Mechanically integrated components on mount members or optical micro-benches

Abstract

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

Claims

1. A two-sided-access extended, or embedded, wafer-level ball grid array (TSA eWLB) package comprising:

a mold having a front side and a rear side;

a redistribution layer disposed on front side of the mold, the redistribution layer including layers of metal and layers of dielectric material that are patterned to form predetermined patterns of electrical traces;

at least a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the redistribution layer, the front face of the die having at least a first electrical contact pad disposed thereon that is in contact with the redistribution layer;

a first metal stamp disposed on a rear face of the first IC die, wherein a portion of the metal stamp is exposed through the rear side of the mold, the rear face of the die having at least a first electrical contact pad disposed thereon that is in contact with the first metal stamp, and wherein the first IC die is free of any electrical connection through the first IC die between the metal stamp and the first electrical contact pad disposed on the front face of the die, and is free of any electrical connection through the first IC die between the first electrical contact pad disposed on the rear face of the die and the first electrical contact pad disposed on the front face of the die;

at least a first solder ball disposed on the exposed portion of the metal stamp;

at least a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the redistribution layer;

a second metal stamp disposed on a rear face of the second IC die, wherein a portion of the second metal stamp is exposed through the rear side of the mold;

at least a second solder ball disposed on the exposed portion of the second metal stamp; and

at least a first thru-via (TV) comprising a hole that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first TV is located on the rear side of the mold and a second end of the first TV is located on the front side of the mold; and

at least a third solder ball disposed on the first end of the first TV wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a first electrical trace of the redistribution layer.

2. The TSA eWLB package of claim 1, wherein the first and second IC dies are of different types.

3. The TSA eWLB package of claim 1, wherein the second IC die has at least a first electrical contact pad disposed on the front faces thereof, and wherein the first electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by a second electrical trace of the redistribution layer.

4. The TSA eWLB package of claim 1, wherein:

the first thru-via (TV) comprises a first thru-mold via (TMV) formed in the mold.

5. The TSA eWLB package of claim 1, wherein the second IC die is a silicon die, and wherein:

the first thru-via (TV) comprises a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die;

a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and

wherein the third solder ball is disposed on the first TSV electrical contact.

6. The TSA eWLB package of claim 5, wherein the second end of the first TSV is electrically connected to the second electrical contact pad disposed on the front face of the second IC die by the first second electrical trace of the redistribution layer.

7. The TSA eWLB package of claim 1, further comprising:

an optical element formed in a portion of the redistribution layer that is located adjacent the front face of the first IC die.

8. The TSA eWLB package of claim 7, wherein the optical element is a refractive lens.

9. The TSA eWLB package of claim 7, wherein the optical element is a Fresnel lens.

10. The TSA eWLB package of claim 7, wherein the optical element is a holographic element.

11. A two-sided-access extended, or embedded, wafer-level ball grid array (TSA eWLB) assembly comprising:

a TSA eWLB package comprising;

a mold having a front side and a rear side,

a redistribution layer disposed on front side of the mold, the redistribution layer including layers of metal and layers of dielectric material that are patterned to form predetermined patterns of electrical traces,

at least a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the redistribution layer, the front face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the redistribution layer,

a first metal stamp disposed on a rear face of the first IC die, wherein a portion of the metal stamp is exposed through the rear side of the mold, the rear face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the first metal stamp, and wherein the first IC die is free of any electrical connection through the first IC die between the metal stamp and the first electrical contact pad disposed on the front face of the die, and is free of any electrical connection through the first IC die between the first electrical contact pad disposed on the rear face of the die and the first electrical contact pad disposed on the front face of the die, and

at least a first solder ball disposed on the exposed portion of the metal stamp,

at least a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the redistribution layer;

a second metal stamp disposed on a rear face of the second IC die, wherein a portion of the second metal stamp is exposed through the rear side of the mold,

at least a second solder ball disposed on the exposed portion of the second metal stamp,

at least a first thru-via (TV) comprising a hole that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first TV is located on the rear side of the mold and a second end of the first TV is located on the front side of the mold; and

at least a third solder ball disposed on the first end of the first TV wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a first electrical trace of the redistribution layer; and

a printed circuit board (PCB) having an upper surface and a lower surface, the upper surface having electrical contacts disposed thereon, the TSA eWLB package being mounted rear-side down on the upper surface of the PCB such that said at least a first solder ball, second solder ball, and third solder ball of the TSA eWLB package are each in contact with a different one of the electrical contacts disposed on the upper surface of the PCB.

12. The TSA eWLB assembly of claim 11, wherein the first and second IC dies are of different types.

13. The TSA eWLB assembly of claim 11, wherein the second IC die has at least a first electrical contact pad disposed on the front face thereof, and wherein the first electrical contact pads disposed on the front faces of the first and second IC dies are electrically interconnected with one another by a second electrical trace of the redistribution layer.

14. The TSA eWLB assembly of claim 11, wherein the first thru-via (TV) comprises a first thru-mold via (TMV) formed in the mold.

15. The TSA eWLB assembly of claim 11, wherein the second IC die is a silicon die, and wherein:

the first thru-via (TV) comprises a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die;

a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and

wherein the third solder ball is disposed on the first TSV electrical contact.

16. The TSA eWLB assembly of claim 15, wherein the second end of the first TSV is electrically connected to the second electrical contact pad disposed on the front face of the second IC die by the first electrical trace of the redistribution layer.

17. The TSA eWLB assembly of claim 11, wherein the first IC die is an electrical-to-optical converter and the second IC die is an optical-to-electrical converter, and wherein the assembly further comprises:

a cap secured to the front side of the mold, the cap having first and second optical pathways formed therein, the first and second optical pathways being located above the first and second IC dies, respectively, the first optical pathway directing light emitted by the first IC die in a direction that is away from the first IC die and generally normal to the front face of the first IC die, the second optical pathway directing light that falls onto the assembly and onto the second optical pathway in a direction that is toward the second IC die and generally normal to the front face of the second IC die.

18. A method for providing a two-sided-access extended, or embedded, wafer-level ball grid array (TSA eWLB) assembly comprising:

providing a TSA eWLB package comprising;

a mold having a front side and a rear side,

a redistribution layer disposed on front side of the mold, the redistribution layer including layers of metal and layers of dielectric material that are patterned to form predetermined patterns of electrical traces,

at least a first integrated circuit (IC) die disposed inside of the mold such that a front face of the first IC die is in contact with the redistribution layer, the front face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the redistribution layer,

a first metal stamp disposed on a rear face of the first IC die, wherein a portion of the metal stamp is exposed through the rear side of the mold, the rear face of the first IC die having at least a first electrical contact pad disposed thereon that is in contact with the first metal stamp, and wherein the first IC die is free of any electrical connection through the first IC die between the metal stamp and the first electrical contact pad disposed on the front face of the die, and is free of any electrical connection through the first IC die between the first electrical contact pad disposed on the rear face of the die and the first electrical contact pad disposed on the front face of the die,

at least a first solder ball disposed on the exposed portion of the metal stamp,

at least a second IC die disposed inside of the mold such that a front face of the second IC die is in contact with the redistribution layer,

a second metal stamp disposed on a rear face of the second IC die, wherein a portion of the second metal stamp is exposed through the rear side of the mold,

at least a second solder ball disposed on the exposed portion of the second metal stamp,

at least a first thru-via (TV) comprising a hole that extends from the rear side of the mold to the front side of the mold and that is filled with an electrically-conductive material, wherein a first end of the first TV is located on the rear side of the mold and a second end of the first TV is located on the front side of the mold, and

at least a third solder ball disposed on the first end of the first TV wherein the third solder ball is electrically connected to a second electrical contact pad disposed on the front face of the first IC die by a first electrical trace of the redistribution layer; and

mounting the TSA eWLB package rear-side down on an upper surface of a printed circuit board (PCB) such that said at least a first solder ball, second solder ball, and third solder ball of the TSA eWLB package are each in contact with a respective one of a plurality of electrical contacts disposed on the upper surface of the PCB.

19. The method of claim 18, wherein the first and second IC dies are of different types.

20. The method of claim 18, wherein the second IC die has at least a first electrical contact pad disposed on the front faces thereof, and wherein the first electrical contacts disposed on the front faces of the first and second IC dies are electrically interconnected with one another by a second electrical trace of the redistribution layer.

21. The method of claim 18, wherein:

the first thru-via (TV) comprises a first thru-mold via (TMV) formed in the mold.

22. The method assembly of claim 18, wherein the second IC die is a silicon die, and wherein:

the first thru-via (TV) comprises a first thru-silicon via (TSV) formed in the second IC die, the first TSV comprising a hole that extends from the rear face of the second IC die to the front face of the second IC die and that is filled with an electrically-conductive material, wherein a first end of the first TSV is located on the rear face of the second IC die and a second end of the first TSV is located on the front face of the second IC die;

a first TSV electrical contact disposed on the rear face of the second IC die in contact with the first end of the first TSV; and

wherein the third solder ball is disposed on the first TSV electrical contact.

23. The method of claim 22, wherein the second end of the first TSV is electrically connected to the second electrical contact pad disposed on the front face of the second IC die by the first electrical trace of the redistribution layer.