Monolithic three dimensional integration of semiconductor integrated circuits

• US 9,177,890 B2
• Filed: 03/07/2013
• Issued: 11/03/2015
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Du, Yang
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/788,224
• Publication Number:
  US 20140252306A1
• Time in Patent Office: 971 Days
• Field of Search: 257/9, 257/24, 257/355, 257/335, 257/278, 257/659, 438/455, 438/141, 438/4, 438/479, 438/283, 438/142
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/762 : Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Abstract

A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

Claims

1. An apparatus comprising:

a silicon substrate;

a bottom tier on the silicon substrate, the bottom tier comprising a plurality of transistors wherein each transistor in the plurality of transistors in the bottom tier comprises a source, a drain and a gate, and wherein the silicon substrate has at least one bottom tier via connected to at least one of the source, drain and gate of at least one of the transistors in the bottom tier;

a thin oxide layer on the bottom tier, the thin oxide layer having at least one inter-tier via; and

a top tier on the thin oxide layer, the top tier comprising a plurality of nanowire transistors, wherein each nanowire transistor in the plurality of nanowire transistors comprises a source, a drain, a gate and a channel, wherein the top tier has at least one top tier via connected to at least one of the source, drain and gate of at least one of the nanowire transistors in the top tier, and wherein the channel has a doping concentration equal to 10¹⁸ cm<sup>−

3</sup> and less than that of the source and the drain; and

at least one interconnect comprising said at least one bottom tier via, said at least one top tier via and said at least one inter-tier via to connect the source or the drain of the at least one of the transistors in the bottom tier to the source or drain of the at least one of the nanowire transistors in the top tier and the gate of at least another one of the nanowire transistors in the top tier.

2. The apparatus of claim 1, wherein the source and drain for each nanowire transistor in the plurality of nanowire transistors is formed by in-situ doping during epitaxial growth at a temperature equal to or less than 450°

C.

3. The apparatus of claim 1, wherein the source and drain for each nanowire transistor in the plurality of nanowire transistors have a doping concentration equal to or greater than 10²⁰ cm⁻

3.

4. The apparatus of claim 1, wherein the plurality of transistors comprises pMOSFETs (p-Metal-Oxide-Semiconductor-Field-Effect-Transistor) and nMOSFETs.