Active matrix substrate and liquid crystal display panel including the same, and method for manufacturing active matrix substrate with gate insulating film not provided where auxiliary capacitor is provided

• US 9,177,974 B2
• Filed: 07/26/2010
• Issued: 11/03/2015
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Chikama, Yoshimasa, Nishiki, Hirohiko, Ohta, Yoshifumi, Hara, Takeshi, Aita, Tetsuya, Suzuki, Masahiko, Takei, Michiko, Nakagawa, Okifumi, Harumoto, Yoshiyuki, Mizuno, Yuuiji
• Primary Examiner(s): NGO, HUYEN LE
• Application Number:
  US13/501,534
• Publication Number:
  US 20120218485A1
• Time in Patent Office: 1,926 Days
• Field of Search: 349 39- 43, 257/71, 257/E33.053, 257/E29.273, 438/23
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).

Claims

1. An active matrix substrate comprising:

a plurality of pixels arranged in a matrix;

a plurality of capacitor lines extending in one of directions in which the pixels are aligned and in parallel to each other;

a plurality of thin film transistors, one for each of the pixels;

a protective film covering the thin film transistors;

a plurality of pixel electrodes arranged in a matrix on the protective film and connected to the respective corresponding thin film transistors; and

a plurality of auxiliary capacitors, one for each of the pixels, wherein

each of the auxiliary capacitors includes the corresponding capacitor line, the corresponding pixel electrode, and the protective film between the corresponding capacitor line and the corresponding pixel electrode, and

in a portion in which each of the plurality of auxiliary capacitors is provided, a gate insulating film forming each of the plurality of thin film transistors is not provided.

2. The active matrix substrate of claim 1, wherein

a gate line connected to a corresponding one of the plurality of thin film transistors is provided between adjacent ones of the capacitor lines and extends along a corresponding one of the plurality of capacitor lines.

3. A method for manufacturing the active matrix substrate of claim 2, comprising:

a gate layer forming step of forming, on a substrate, the plurality of capacitor lines and the gate lines;

a semiconductor layer forming step of forming a first insulating film covering the capacitor lines and the gate lines, and thereafter, forming a plurality of semiconductor layers, which form the respective corresponding one of the plurality of thin film transistors, directly above the respective corresponding gate lines;

a gate insulating film forming step of removing a portion of the first insulating film to expose each of the capacitor lines, thereby forming a gate insulating film;

a source layer forming step of forming a source electrode and a drain electrode, which form each of the plurality of thin film transistors, on each of the semiconductor layers;

a protective film forming step of forming a second insulating film covering the source electrodes and the drain electrodes, and thereafter, removing a portion of the second insulating film to expose of a portion of each of the drain electrodes, thereby forming a protective film; and

a pixel electrode forming step of forming a plurality of pixel electrodes arranged in a matrix on the protective film, thereby forming a plurality of auxiliary capacitors each including the corresponding capacitor line, the protective film, and the corresponding pixel electrode.

4. The method of claim 3, wherein

in the protective film forming step, a portion of the protective film which is included in each of the auxiliary capacitors is thinner than a portion of the protective film which covers the source and drain electrodes.

5. The method of claim 4, wherein

the protective film forming step includes a resist pattern forming step of forming a photosensitive resin film on the second insulating film, and thereafter, performing a halftone exposure on the photosensitive resin film to form a resist pattern having recessed portions at each of which the corresponding auxiliary capacitor is to be formed, a first etching step of etching the second insulating film exposed through the resist pattern formed in the resist pattern forming step, and a second etching step of reducing a thickness of the resist pattern used in the first etching step by ashing to remove a bottom portion of the recessed portion of the resist pattern, thereby exposing the second insulating film, and etching an upper layer portion of the exposed second insulating film.

6. The method of claim 3, wherein

in the gate insulating film forming step, a channel protective layer is formed on each of the semiconductor layers.

7. The active matrix substrate of claim 1, wherein

each of the capacitor lines is a gate line.

8. The active matrix substrate of claim 1, wherein

a portion of the protective film which is included in each of the auxiliary capacitors is thinner than a portion of the protective film which covers each of the thin film transistors.

9. The active matrix substrate of claim 1, wherein

each of the auxiliary capacitors includes a conductive layer which is provided between the corresponding capacitor line and the protective film, and is provided in the same layer in which the source and drain electrodes of the corresponding thin film transistor are provided and is formed of the same material of which the source and drain electrodes of the corresponding thin film transistor are formed.

10. The active matrix substrate of claim 1, wherein

each of the thin film transistors includes an oxide semiconductor layer.

11. The active matrix substrate of claim 10, wherein

the oxide semiconductor layer is an In—

Ga—

Zn—

O oxide semiconductor layer.

12. A liquid crystal display panel comprising:

an active matrix substrate and a counter substrate facing each other; and

a liquid crystal layer provided between the active matrix substrate and the counter substrate, with a plurality of pixels being arranged in a matrix,

wherein

the active matrix substrate includes

a plurality of capacitor lines extending in one of directions in which the pixels are aligned and in parallel to each other;

a plurality of thin film transistors, one for each of the pixels;

a protective film covering the thin film transistors;

a plurality of pixel electrodes arranged in a matrix on the protective film and connected to the respective corresponding thin film transistors; and

a plurality of auxiliary capacitors, one for each of the pixels,

each of the auxiliary capacitors includes the corresponding capacitor line, the corresponding pixel electrode, and the protective film between the corresponding capacitor line and the corresponding pixel electrode, and

in a portion in which each of the plurality of auxiliary capacitors is provided, a gate insulating film forming each of the plurality of thin film transistors is not provided.