Trench MOS device having a termination structure with multiple field-relaxation trenches for high voltage applications

• US 9,178,015 B2
• Filed: 01/10/2014
• Issued: 11/03/2015
• Est. Priority Date: 01/10/2014
• Status: Active Grant

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Chang, Chun-Chueh, Lin, Yi-Yu, Kung, Pu Ju
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US14/152,564
• Publication Number:
  US 20150200250A1
• Time in Patent Office: 662 Days
• Field of Search: 257/330, 257/329, 257/328, 257/341, 257/335, 257/E29.256, 257/E27.06, 257/E21.41, 438/268, 438/270, 438/589
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A termination structure for a semiconductor device includes a semiconductor substrate having an active region and a termination region. Two or more trench cells are located in the termination region and extend from a boundary of the active region toward an edge of the semiconductor substrate. A termination trench is formed in the termination region on a side of the trench cells remote from the active region. A conductive spacer is located adjacent to a sidewall of the termination trench nearest the trench cells. A first oxide layer is formed in the termination trench and contacts a sidewall of the conductive spacer. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.

Claims

1. A termination structure for a semiconductor device, said termination structure comprising:

a semiconductor substrate having an active region and a termination region;

a plurality of trench cells located only in the termination region and extending from a boundary of the active region toward an edge of the semiconductor substrate;

a termination trench formed in the termination region on a side of the plurality of trench cells remote from the active region;

a conductive spacer located adjacent a sidewall of the termination trench nearest the plurality of trench cells;

a first oxide layer formed in the termination trench and contacting a sidewall of the conductive spacer;

a first conductive layer formed on a backside surface of the semiconductor substrate;

a second conductive layer formed atop the active region and the termination region wherein the plurality of trench cells are filled with a conductive material up to a top surface of a plurality of mesas;

wherein the second conductive layer extends from the active area as a continuous layer and completely covering the plurality of trench cells and at least a portion of the termination trench such that the second conductive layer, the conductive spacer and a field plate formed in the termination region are electrically coupled to one another.

2. The termination structure of claim 1, further comprising a second oxide layer lining sidewalls and a bottom surface of the trench cells and the termination trench, the conductive spacer being in contact with the second oxide layer on a sidewall and bottom surface of the termination trench.

3. The termination structure of claim 2, further comprising a third oxide layer located on the mesas disposed between adjacent trench cells and being further located between the second conductive layer and the semiconductor substrate.

4. The termination structure of claim 3, wherein said Schottky diode is a TMBS Schottky diode that includes at least one trench in the active region of the substrate.

5. The termination structure of claim 1, wherein said semiconductor device is a Schottky diode.

6. The termination structure of claim 1, wherein said termination structure is employed in a device selected from the group consisting of power transistors and rectifiers.

7. A semiconductor device, comprising:

a semiconductor substrate having at least one trench MOS device located in an active region of the semiconductor substrate;

a plurality of trench cells only located in a termination region of the semiconductor substrate adjacent to the active region of the semiconductor substrate, the plurality of trench cells extending from a boundary between the active and termination regions toward an edge of the semiconductor substrate;

a termination trench formed in the termination region on a side of the plurality of trench cells remote from the active region;

a first oxide layer lining the plurality of trench cells and the termination trench;

a conductive spacer located adjacent a sidewall of the termination trench nearest the plurality of trench cells;

a second oxide layer formed in the termination trench and contacting a sidewall of the conductive spacer;

a first conductive layer formed on a backside surface of the semiconductor substrate; and

a second conductive layer located atop the active region and the termination region, a portion of the second conductive layer located in the termination region defining a field plate.

8. The semiconductor device of claim 7, wherein said semiconductor substrate comprises a first layer and a base substrate, and said first layer has a first type of conductive impurities lightly doped and said base substrate has said first type of conductive impurities heavily doped.

9. The semiconductor device of claim 7, wherein said trench MOS devices and said termination trench are formed in said first layer and have a depth of between about 0.5-10.0 microns.

10. The semiconductor device of claim 7, wherein said termination trench has a width between about 10-50 microns.

11. The semiconductor device of claim 7, further comprising a third oxide layer located on mesas disposed between adjacent trench cells and being further located between the second conductive layer and the semiconductor substrate.

12. The semiconductor device of claim 7, wherein said semiconductor device is a Schottky diode.

13. The semiconductor device of claim 12, wherein said Schottky diode is a TMBS Schottky diode that includes at least one trench in the active region of the substrate.

14. The semiconductor device of claim 7 wherein said trench cells are filled with a conductive material.

15. The semiconductor device of claim 7 wherein the second conductive layer extends as a continuous layer that extends into the trench cells and at least a portion of the termination trench such that the second conductive layer and the conductive spacer are electrically coupled to one another.

16. The semiconductor device of claim 7, wherein said termination structure is employed in a device selected from the group consisting of power transistors and rectifiers.

17. A method of forming a semiconductor device, comprising:

forming at least one trench MOS device located in an active region of a semiconductor substrate,

forming a plurality of trench cells located in a termination region of the semiconductor substrate adjacent to the active region of the semiconductor substrate,

the plurality of trench cells extending from a boundary between the active and termination regions toward an edge of the semiconductor substrate,

forming a termination trench in the termination region of the semiconductor substrate on a side of the plurality of trench cells remote from the active region,

forming a conductive spacer located adjacent a sidewall of the termination trench nearest the plurality of trench cells, forming a first oxide layer in the termination trench which contacts a sidewall of the conductive spacer,

forming a first conductive layer on a backside surface of the semiconductor substrate,

forming a second conductive layer located atop the active region; and

forming a first conductive layer on a backside surface of the semiconductor substrate,

wherein the plurality of trench cells are filled with a conductive material up to a top surface of a plurality of mesas, wherein the second conductive layer extends from the active area as a continuous layer and completely covering the plurality of trench cells and at least a portion of the termination trench such that the second conductive layer, the conductive spacer and a field plate formed in the termination region are electrically coupled to one another.

18. The method of claim 17 wherein forming the field plate includes forming an extension of the second conductive layer into the termination trench.