Power MOSFET and methods for forming the same

• US 9,178,041 B2
• Filed: 12/17/2014
• Issued: 11/03/2015
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): BRADLEY, STEPHEN M
• Application Number:
  US14/574,096
• Publication Number:
  US 20150104917A1
• Time in Patent Office: 321 Days
• Field of Search: 257/330, 257/339, 257/499, 257/500, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.

Claims

1. A method comprising:

forming a first trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;

forming an implantation mask extending into the trench and covering edges of the trench;

performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type;

etching the semiconductor region and a bottom portion of the DD region to extend the trench further down into the semiconductor region, wherein the etching is anisotropic, with portions of the DD region located on opposite sides of the trench;

after the etching, forming a first dielectric layer lining a bottom and sidewalls of the trench;

forming a field plate in the trench and over a bottom portion of the first dielectric layer;

forming a second dielectric layer over the field plate;

forming a main gate in the trench and over the second dielectric layer; and

forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.

2. The method of claim 1, wherein the forming the second dielectric layer comprises:

filling the trench with a dielectric material; and

etching back the dielectric material, wherein portions of the first dielectric layer level with etched portions of the dielectric material are removed in the etching back.

3. The method of claim 1 further comprising:

after the forming the second dielectric layer and before the forming the main gate, removing the implantation mask.

4. The method of claim 1 further comprising:

before the forming the implantation mask, forming an additional dielectric layer lining the trench, wherein the additional dielectric layer is between and contacting a sidewall of the main gate and an edge of the semiconductor region.

5. The method of claim 4 further comprising performing an implantation to form a body region in the semiconductor region, wherein the body region comprises a bottom lower than a bottom of the additional dielectric layer.

6. The method of claim 1, wherein the main gate comprises a portion overlapping a portion of the DD region, with the portion of the DD region having a first impurity concentration of the first conductivity type higher than a second impurity concentration of the semiconductor region.

7. The method of claim 6, wherein the portion of the DD region overlapped by the main gate comprises an edge contacting a sidewall of the first dielectric layer.

8. The method of claim 1, wherein the etching the semiconductor region is performed before the tilt implantation, and the method further comprises:

before the tilt implantation and after the etching the semiconductor region, forming an additional implantation mask to cover a bottom of the trench, with the tilt implantation performed through the additional implantation mask, wherein the additional implantation mask has a top surface lower than a top surface of the trench; and

after the tilt implantation, removing the additional implantation mask.

9. The method of claim 1, wherein the etching the semiconductor region to extend the trench is performed after the tilt implantation.

10. The method of claim 1, wherein the forming the main gate comprises:

forming a first portion of the main gate before the implantation, with the implantation performed using the first portion as a part of a mask; and

after the second dielectric layer is formed, forming a second portion of the main gate.

11. A method comprising:

epitaxially growing an epitaxy semiconductor region of a first conductivity type;

forming a first trench in the epitaxy semiconductor region;

forming an implantation mask extending into the trench and covering edge portions of the trench;

forming an additional implantation mask to cover a bottom of the trench, wherein the additional implantation mask has a top surface lower than a top surface of the trench;

performing a tilt implantation through the implantation mask and the additional implantation mask to form a Doped Drain (DD) region in the epitaxy semiconductor region, wherein the DD region comprises portions overlapped by the implantation mask, and wherein the DD region is of a first conductivity type;

etching the epitaxy semiconductor region to extend the trench further down into the epitaxy semiconductor region, wherein the etching is performed using the implantation mask as an etching mask;

after the etching, forming a first dielectric layer lining the trench;

forming a field plate in the trench and over the first dielectric layer, wherein the field plate comprises a bottom and sidewalls contacting the first dielectric layer;

forming a second dielectric layer over the field plate;

forming a main gate in the trench and over the second dielectric layer; and

forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.

12. The method of claim 11 further comprising:

forming a source region over the epitaxy semiconductor region; and

forming a drain region under the epitaxy semiconductor region, wherein the source region, the drain region, the DD region, the field plate, and the main gate form a power Metal-oxide-Semiconductor Field Effect Transistor (MOSFET).

13. The method of claim 11, wherein the DD region is formed after the epitaxy semiconductor region is etched.

14. The method of claim 11, wherein the forming the DD region is performed before the etching the epitaxy semiconductor region to extend the trench.

15. The method of claim 11, wherein the forming the main gate comprises:

forming a first portion of the main gate before the implantation, with the implantation performed using the first portion as a part of a mask; and

after the second dielectric layer is formed, forming a second portion of the main gate.

16. The method of claim 11, wherein in the etching the epitaxy semiconductor region to extend the trench, a portion of the DD region is etched.

17. A method comprising:

forming a field plate in a semiconductor region of a first conductivity type;

forming a first dielectric layer comprising first portions on opposite sides of the field plate, and second portions underlying the field plate;

forming Doped Drain (DD) regions on opposite sides of the first dielectric layer, wherein the DD region is of the first conductivity type;

performing an implantation to form a body region in the semiconductor region, wherein the body region is of a second conductivity type opposite to the first conductivity type;

forming a second dielectric layer over the field plate;

forming a main gate over the second dielectric layer, wherein the DD regions comprise a portion overlapped by the main gate, and the portion of the DD regions comprises a sidewall contacting a sidewall of the first dielectric layer, and the forming the main gate comprises;

forming a first portion of the main gate before the implantation, with the implantation performed using the first portion as a part of a mask; and

after the second dielectric layer is formed, forming a second portion of the main gate; and

forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.

18. The method of claim 17, wherein the forming the DD regions comprises:

performing an implantation on the semiconductor region to form a continuous DD region; and

etching the semiconductor region to form a trench penetrating through the continuous DD region.

19. The method of claim 17 further comprising forming a source region and a drain region on opposite sides of the semiconductor region, wherein the source region and the drain region are configured to be connected through a channel in the body region.

20. The method of claim 17 further comprising:

etching the semiconductor region to form a trench; and

forming an implantation mask to cover a bottom of the trench, wherein the implantation mask has a top surface lower than a top surface of the trench, and the DD region is formed by an additional implantation through the implantation mask.