Structure and method for FinFET device

• US 9,178,067 B1
• Filed: 08/13/2014
• Issued: 11/03/2015
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Fung, Ka-Hing, Chang, Chih-Sheng, Wu, Zhiqiang
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/458,484
• Publication Number:
  US 20150311336A1
• Time in Patent Office: 447 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 : Field effect transistors
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

Claims

1. A fin-like field-effect transistor (FinFET) device comprising:

a substrate having a first gate region;

a first fin structure over the substrate in the first gate region, the first fin structure including;

an upper semiconductor material member;

a lower semiconductor material member, surrounded by an oxide feature; and

a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member; and

a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member,

wherein the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

2. The device of claim 1, further comprising:

a first high-k/metal gate stack wraps over the upper semiconductor material member, including wrapping over the middle portion of the upper semiconductor material member.

3. The device of claim 1, wherein the liner includes one or more materials from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide.

4. The device of claim 1, wherein:

a top surface of the dielectric layer is above a top surface of the liner at a distance in a range of about 3 nm to about 10 nm; and

the top surface of the dielectric layer is above a top surface of the lower semiconductor member at a distance in a range of about 5 nm to about 20 nm.

5. The device of claim 1, wherein the liner is deposited by atomic layer deposition (ALD), with a thickness in a range of about 20 Å

to about 60 Å

.

6. The device of claim 1, wherein:

the upper semiconductor material member includes epitaxial silicon (Si);

the lower semiconductor material member includes epitaxial silicon germanium (SiGe); and

the oxide feature includes silicon germanium oxide (SiGeO).

7. The device of claim 1, wherein the liner includes a first layer wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member;

and a second layer wraps over the first layer.

8. The device of claim 7, wherein:

the first layer includes one or more materials from the group consisting of silicon and silicon oxynitride;

the second layer includes one or more materials from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide;

the first layer has a thickness in a range of about 10 Å

to about 30 Å

;

the second layer has a thickness in a range of about 20 Å

to about 60 Å

;

a top surface of the first layer is below or at same level of a top surface of the dielectric layer; and

a top surface of the second layer is below the top surface of the dielectric layer at a distance in a range of about 3 nm to about 10 nm.

9. The device of claim 1, Further comprising:

a second fin structure over the substrate, in a second gate region, the second fin structure including;

an upper semiconductor material member;

a middle semiconductor material member; and

a lower semiconductor material member;

the liner wrapping around the lower semiconductor material member and the middle semiconductor member, and extending upwards to wrap around a lower portion of the upper semiconductor material member;

the dielectric layer laterally proximate to an upper portion of the middle semiconductor material member,

wherein the middle semiconductor material member includes an upper portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner; and

a second high-k/metal gate stack over the substrate, including wrapping over the upper semiconductor material member and the upper portion of the middle semiconductor material member in the second gate region.

10. The device of claim 9, wherein:

the upper semiconductor material member includes epitaxial silicon germanium (SiGe);

the middle semiconductor material member includes epitaxial silicon (Si); and

the lower semiconductor material member includes epitaxial SiGe.

11. The device of claim 9, further comprising:

second source and drain (S/D) regions separated by the second gate region over the substrate;

the second fin structure having a recessed upper semiconductor material member in the second S/D regions; and

second source/drain features on top of the recessed upper semiconductor material member.

12. The device of claim 1, further comprising:

first source and drain (S/D) regions separated by the first gate region over the substrate;

the first fin structure having a recessed upper semiconductor material member in the first S/D regions; and

first source/drain features on top of the recessed upper semiconductor material member.

13. A fin-like field-effect transistor (FinFET) device comprising:

a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;

a first fin structure over the substrate in the NFET region, the first fin structure including;

an epitaxial silicon (Si) layer as its upper portion; and

an epitaxial silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its lower portion;

a liner wrapping around the SiGeO feature, and extending upwards to wrap around a lower portion of the Si layer; and

a dielectric layer laterally proximate to an upper portion of the Si layer, wherein the upper Si layer includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner,

a second fin structure over the substrate in the PFET region, the second fin structure including;

an epitaxial SiGe layer as its upper portion;

an epitaxial Si as its middle portion; and

another epitaxial SiGe layer as its bottom portion;

the liner wrapping around the lower SiGe layer and the middle Si layer, and extending upwards to wrap around a lower portion of the upper SiGe layer; and

the dielectric layer laterally proximate to an upper portion of the upper SiGe layer, wherein the upper SiGe layer includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

14. The device of claim 13, wherein the liner includes one or more materials from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide.

15. The device of claim 13, wherein the liner is deposited by atomic layer deposition (ALD), with a thickness in a range of about 20 Å

to about 60 Å

.

16. The device of claim 13, wherein:

a top surface of the dielectric layer is above a top surface of the liner at a distance in a range of about 3 nm to about 10 nm; and

the top surface of the dielectric layer is above a top surface of the lower SiGe layer at a distance in a range of about 5 nm to about 20 nm.

17. The device of claim 13, further comprising:

a first gate region in a portion of the first fin structure;

a first high-k/metal gate stack over the substrate, including wrapping over a portion of the upper Si layer of the first fin structure;

first source and drain (S/D) regions separated by the first gate region over the substrate;

first source/drain features on top of the recessed upper Si layer in the first S/d regions;

a second gate region in a portion of the second fin structure;

a second high-k/metal gate stacks over the substrate, including wrapping over a portion of the upper SiGe layer of the second fin structure;

second S/D regions separated by the second gate region over the substrate; and

second source/drain features on top of the recessed upper SiGe layer.