Light emitting device reflective bank structure

• US 9,178,123 B2
• Filed: 12/10/2012
• Issued: 11/03/2015
• Est. Priority Date: 12/10/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Sakariya, Kapil V., Bibl, Andreas, Hu, Hsin-Hua
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/710,443
• Publication Number:
  US 20140159064A1
• Time in Patent Office: 1,058 Days
• Field of Search: 257/88, 313501-506
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.

Claims

1. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices has a maximum width of 1 μ

m-100 μ

m and includes a micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers, and wherein the micro p-n diode includes one or more layers based on II-VI materials or III-V materials;

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer; and

a transparent passivation layer spanning sidewalls of the array of vertical light emitting diode devices and least partially filling the array of bank openings.

2. The reflective bank structure of claim 1, wherein each of the bank openings has a maximum width of 1 μ

m-100 μ

m.

3. The reflective bank structure of claim 1, wherein a top surface of each vertical light emitting diode device is above a top surface of the insulating layer.

4. The reflective bank structure of claim 1, wherein each vertical light emitting diode device comprises a top conductive electrode and a bottom conductive electrode.

5. The reflective bank structure of claim 4, wherein no vertical light emitting diode device spans along a sidewall of a corresponding bank opening.

6. The reflective bank structure of claim 1,

wherein each vertical light emitting diode device comprises a top conductive electrode and a bottom conductive electrode;

and

wherein the transparent passivation layer does not completely cover the top conductive electrode of each vertical light emitting diode device.

7. The reflective bank structure of claim 6, further comprising a transparent conductor layer over and in electrical contact with the top conductive electrode for each vertical light emitting diode device.

8. The reflective bank structure of claim 1, wherein the reflective layer completely covers the sidewalls of each of the bank openings.

9. The reflective bank structure of claim 8, wherein the reflective layer completely covers the bottom surface of each of the bank openings.

10. The reflective bank structure of claim 9, wherein the reflective layer is a continuous layer formed over the insulating layer and on the substrate within the array of bank openings in the insulating layer.

11. The reflective bank structure of claim 1, wherein the substrate is a lighting substrate.

12. The reflective bank structure of claim 1, wherein the substrate is a display substrate.

13. The reflective bank structure of claim 1, further comprising an integrated circuit within the substrate.

14. The reflective bank structure of claim 13, further comprising a corresponding array of integrated circuits interconnected with the bottom surfaces of the array of bank openings.

15. The reflective bank structure of claim 1, further comprising an electrical line out at the bottom surfaces of the array of bank openings.

16. The reflective bank structure of claim 1, further comprising a corresponding array of electrical lines out at the bottom surfaces of the array of bank openings.

17. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls characterized by a first and second laterally opposite sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices includes a micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers; and

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer;

wherein the reflective layer is a patterned layer comprising an array of reflective bank layers corresponding to the array of bank openings, wherein each reflective bank layer in the array of reflective bank layers spans the first laterally opposite sidewall and does not span the second laterally opposite sidewall of a corresponding bank opening, and each reflective bank layer does not completely cover the bottom surface of the corresponding bank opening.

18. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices has a maximum width of 1 μ

m-100 μ

m and includes a top conductive electrode, a bottom conductive electrode, and micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers, and wherein the micro p-n diode includes one or more layers based on II-VI materials or III-V materials;

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer;

one or more integrated circuits in the substrate and in electrical contact with the bottom conductive electrodes of the array of vertical light emitting diode devices; and

an electrical line out on the insulating layer and in electrical contact with the top conductive electrode of each vertical light emitting diode device.

19. The reflective bank structure of claim 18,

wherein the reflective layer is a patterned layer comprising an array of reflective bank layers corresponding to the array of bank openings, wherein each reflective bank layer spans the sidewalls of a corresponding bank opening, and

wherein the patterned layer comprises the array of reflective bank layers within the array of bank openings and the electrical line out on the insulating layer.

20. The reflective bank structure of claim 18 further comprising a transparent conductor layer over and in electrical contact with the electrical line out and the top conductive electrode of each vertical light emitting diode device.

21. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices has a maximum width of 1 μ

m-100 μ

m and includes a top conductive electrode, a bottom conductive electrode, and micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers, and wherein the micro p-n diode includes one or more layers based on II-VI materials or III-V materials;

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer;

one or more integrated circuits in the substrate and in electrical contact with the bottom conductive electrodes of the array of vertical light emitting diode devices;

a via opening in the insulating layer; and

an electrical line out at a bottom surface of the via opening and in electrical contact with the top conductive electrode of each vertical light emitting diode device.

22. The reflective bank structure of claim 21, further comprising a transparent conductor layer over and in electrical contact with the electrical line out and the top conductive electrode of each vertical light emitting diode device.

23. The reflective bank structure of claim 22,

wherein the reflective layer is a patterned layer comprising an array of reflective bank layers corresponding to the array of bank openings, wherein each reflective bank layer spans the sidewalls of a corresponding bank opening, and

wherein the patterned layer comprises the array of reflective bank layers within the array of bank openings and a separate reflective via layer within the via opening.

24. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices has a maximum width of 1 μ

m-100 μ

m and includes a top conductive electrode, a bottom conductive electrode, and micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers, and wherein the micro p-n diode includes one or more layers based on II-VI materials or III-V materials;

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer;

one or more integrated circuits in the substrate and in electrical contact with the bottom conductive electrodes of the array of vertical light emitting diode devices; and

an array of electrical lines out on the insulating layer, the array of electrical lines out in electrical contact with the top conductive electrodes of the array of vertical light emitting diode devices.

25. The reflective bank structure of claim 24,

wherein the reflective layer is a patterned layer comprising an array of reflective bank layers corresponding to the array of bank openings, wherein each reflective bank layer spans the sidewalls of a corresponding bank opening, and

wherein the patterned layer comprises the array of reflective bank layers within the array of bank openings and the array of electrical lines out on the insulating layer.

26. The reflective bank structure of claim 24 further comprising an array of transparent conductor layers, each transparent conductor layer over and in electrical contact with a corresponding electrical line out and a top conductive electrode of a corresponding vertical light emitting diode device.

27. A reflective bank structure comprising:

a substrate;

an insulating layer on the substrate;

an array of bank openings in the insulating layer, each bank opening including a bottom surface and sidewalls;

a corresponding array of vertical light emitting diode devices mounted within the array of bank openings, wherein each vertical light emitting diode device in the array of vertical light emitting diode devices has a maximum width of 1 μ

m-100 μ

m and includes a top conductive electrode, a bottom conductive electrode, and micro p-n diode that includes a top p-doped or n-doped layer, a lower p-doped or n-doped layer, and one or more quantum well layers between the top and lower p-doped or n-doped layers, and wherein the micro p-n diode includes one or more layers based on II-VI materials or III-V materials;

a reflective layer spanning the sidewalls of each of the bank openings in the insulating layer;

one or more integrated circuits in the substrate and in electrical contact with the bottom conductive electrodes of the array of vertical light emitting diode devices;

an array of via openings in the insulating layer; and

an array of electrical lines out at bottom surfaces of each of the corresponding array of via openings, the array of electrical lines out in electrical contact with the top conductive electrodes of the array of vertical light emitting diode devices.

28. The reflective bank structure of claim 27, further comprising an array of transparent conductor layers, each transparent conductor layer over and in electrical contact with a corresponding electrical line out and a top conductive electrode of a corresponding vertical light emitting diode device.

29. The reflective bank structure of claim 28,

wherein the reflective layer is a patterned layer comprising an array of reflective bank layers corresponding to the array of bank openings, wherein each reflective bank layer spans the sidewalls of a corresponding bank opening, and

wherein the patterned layer comprises the array of reflective bank layers within the array of bank openings and an array of separate reflective via layers within the array of via openings.