Differential comparator circuit having a wide common mode input range
First Claim
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1. A circuit arrangement, comprising:
- a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier;
for each differential amplifier, a respective adjustable current control circuit coupled to the differential amplifier to limit a tail current passing through the differential amplifier, the adjustable current control circuit being configured to operate in one state of a discrete set of states including fully-on, fully-off, and partially-on, wherein operation of the adjustable current control circuit in the partially-on state causes the differential amplifier to exhibit non-linearity; and
a gain control circuit coupled to the adjustable current control circuits, the gain control circuit configured to adjust, while the adjustable current control circuits for two or more of the plurality of differential amplifiers are operated in respective states other than the fully-off state, the adjustable current control circuits such that only one of the plurality of respective current control circuits can be operated in the partially-on state at a given time, thereby limiting non-linearity exhibited by the plurality of differential amplifiers.
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Abstract
In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit coupled to limit a tail current passing through the differential amplifier.
92 Citations
17 Claims
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1. A circuit arrangement, comprising:
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a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier; for each differential amplifier, a respective adjustable current control circuit coupled to the differential amplifier to limit a tail current passing through the differential amplifier, the adjustable current control circuit being configured to operate in one state of a discrete set of states including fully-on, fully-off, and partially-on, wherein operation of the adjustable current control circuit in the partially-on state causes the differential amplifier to exhibit non-linearity; and a gain control circuit coupled to the adjustable current control circuits, the gain control circuit configured to adjust, while the adjustable current control circuits for two or more of the plurality of differential amplifiers are operated in respective states other than the fully-off state, the adjustable current control circuits such that only one of the plurality of respective current control circuits can be operated in the partially-on state at a given time, thereby limiting non-linearity exhibited by the plurality of differential amplifiers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A differential comparator circuit having a wideband common mode input range, comprising:
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first and second differential input terminals for receiving first and second input signals respectively, a difference between the input signals providing a differential input signal; a plurality of complementary differential pair circuits having inputs coupled to the first and second differential input terminals and each pair having first, second, third, and fourth outputs, the plurality of complementary differential pair circuits including at least first and second complementary differential transistor pair circuits, respectively; a current summation circuit coupled to the first, second, third, and fourth current outputs of the complementary differential pair circuits; a gain control circuit coupled to the complementary differential pair circuits and configured to independently adjust a tail current of each of the plurality of complementary differential transistor pair circuits; wherein the plurality of complementary differential pair circuits are configurable, via the adjustment of the tail currents, to operate in one state of a discrete set of states consisting of fully-on, fully-off, and partially-on; and wherein the gain control circuit is configured to adjust the tail currents such that while two or more of the plurality of complementary differential pair circuits are operated in respective states other than the fully-off state, only one of the plurality of complementary differential pair circuits is operated in the partially-on state at a given time. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An input buffer circuit, comprising:
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a first electrostatic discharge circuit having inputs for receiving a differential signal from a transmission medium; termination resistors coupled to differential outputs of the first electrostatic discharge circuit and configured to match the impedance of the input buffer to the impedance of the transmission medium; a differential comparator circuit coupled to differential output of the termination resistors, the differential comparator circuit including two or more complementary differential pair circuits coupled in parallel; a current summation circuit coupled to outputs of the two or more complementary differential pair circuits; and a gain control circuit coupled and configured to independently adjust a tail current of each of the two or more complementary differential pair circuits such that while two or more of the plurality of complementary differential pair circuits are operated in respective states other than the fully-off state, only one of the plurality of plurality of complementary differential pair circuits is operated in the partially-on state at a given time. - View Dependent Claims (17)
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Specification