N factorial dual data rate clock and data recovery
First Claim
1. A method of data communications, comprising:
- receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval;
generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval;
generating a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval;
using the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and
using the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals.
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Accused Products
Abstract
System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.
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Citations
31 Claims
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1. A method of data communications, comprising:
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receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval; generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval; generating a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval; using the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and using the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 31)
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11. An apparatus, comprising:
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means for receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval; means for generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval; means for generating a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval; means for using the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and means for using the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A receiver, comprising:
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a plurality of line interface circuits configured to receive signals from a plurality of signal wires; and a clock and data recovery circuit configured to; receive a sequence of symbols from the plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval; generate a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval; generate a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval; use the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and use the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals. - View Dependent Claims (22, 23, 24, 25)
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26. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:
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receive a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval; generate a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval; generate a second clock signal from transitions in signaling state of the plurality of signal wires occurring between each even transmission interval and a consecutive odd transmission interval; use the first clock signal to capture a first set of symbols comprising symbols in the sequence of symbols that are received in even transmission intervals; and use the second clock signal to capture a second set of symbols comprising symbols in the sequence of symbols that are received in odd transmission intervals. - View Dependent Claims (27, 28, 29, 30)
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Specification