Systems and methods for preserving the order of data

• US 9,178,840 B2
• Filed: 02/22/2013
• Issued: 11/03/2015
• Est. Priority Date: 10/02/2001
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Lim, Raymond Marcelino Manese, Dyckerhoff, Stefan, Libby, Jeffrey Glenn, Tesfaye, Teshager
• Primary Examiner(s): Kawsar, Abdullah Al
• Application Number:
  US13/774,703
• Publication Number:
  US 20130166856A1
• Time in Patent Office: 984 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: H04L 45/62 Wavelength based optical switching H04Q11/0062
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Claims

1. A method comprising:

receiving, by a device, first data;

assigning, by the device and to the first data, a first address corresponding to a location in a memory,

the memory being an output memory;

transferring, by the device, the first data and the first address to a processor of a plurality of processors of the device;

processing, by the processor of the device, the first data to form processed first data;

storing, by the processor of the device, the processed first data in the memory at the location corresponding to the first address;

receiving, by the device, second data;

assigning, by the device and to the second data, the first address when the first data and the second data are fragments of a same packet; and

assigning, by the device and to the second data, a second address, corresponding to a different location in the memory than the location, when the first data and the second data are not fragments of the same packet.

2. The method of claim 1, where the first address is associated with the processor.

3. The method of claim 1, where assigning the first address corresponding to the location in the memory comprises:

storing the first address in a second location in a second memory; and

reserving the location in the memory based on storing the first address in the second location.

4. The method of claim 3, where the second location in the second memory, with respect to other locations in the second memory, corresponds to the location in the memory, with respect to other locations in the memory.

5. The method of claim 1, further comprising:

receiving the second data after receiving the first data;

assigning, to the second data, the second address corresponding to the different location in the memory, the different location being after the location in the memory;

transferring the second data and the second address to a second processor of the plurality of processors;

processing, by the second processor, the second data to form second processed data; and

storing the second processed data in the memory at the different location corresponding to the second address.

6. The method of claim 1, where transferring the first data and the first address to the processor of the plurality of processors comprises:

receiving a ready signal from the processor when the processor is available to process the first data;

storing the ready signal; and

transferring the first data based on the stored ready signal.

7. The method of claim 1, where transferring the first data and the first address to the processor of the plurality of processors comprises:

receiving ready signals from each processor, of the plurality of processors, that is available to process the first data;

storing the ready signals in an order in which the ready signals are received; and

transferring the first data and the first address to the processor when the ready signal from the processor is stored first.

8. The method of claim 1, further comprising:

determining whether the first data is a fragment of a packet and whether an additional fragment exists in the packet,

the determining being based on analyzing information included in the first data;

requesting the additional fragment based on the first data being a fragment of the packet and the additional fragment existing in the packet; and

where receiving the second data includes receiving the second data based on requesting the additional fragment,

the additional fragment being the second data.

9. A system comprising:

a memory; and

a plurality of processors, a processor of the plurality of processors to;

receive first data and an address assigned to the first data,

the address being associated with the processor, and

the address corresponding to a location in the memory;

process the first data to form first processed data;

output the first processed data to the location in the memory corresponding to the address;

receive second data;

process the second data to generate second processed data; and

selectively output the second processed data to the location in the memory or a different location in the memory based on whether the first data and the second data are fragments of a same packet.

10. The system of claim 9, further comprising:

a dispatcher to assign the address to the first data.

11. The system of claim 10, where the dispatcher is further to:

receive a ready signal from the processor when the processor is available to process the first data;

store the ready signal; and

transfer the first data based on the stored ready signal.

12. The system of claim 10, where the dispatcher is further to:

receive ready signals from each processor, of the plurality of processors, that is available to process the first data;

store the ready signals in an order in which the ready signals are received; and

transfer the first data and the address to the processor when the ready signal from the processor is stored first.

13. The system of claim 9, further comprising:

a second memory; and

a second processor, of the plurality of processors, to;

store the address in a second location in the second memory; and

reserve the location in the memory based on storing the address.

14. The system of claim 13, where the second location in the second memory, with respect to other locations in the second memory, corresponds to the location in the memory, with respect to other locations in the memory.

15. The system of claim 9, where a second processor, of the plurality of processors, is to:

receive third data after the processor receives the first data, the third data being assigned a second address,

the second address being associated with the second processor,

the second address corresponding to a second location in the memory,

the second location being after the location in the memory;

process the third data to form third processed data; and

output the third processed data to the memory at the second location corresponding to the second address.

16. A non-transitory computer-readable medium including instructions, the instructions comprising:

one or more instructions that, when executed by one or more processors, cause the one or more processors to;

receive first data;

assign, to the first data, an address corresponding to a location in a memory,

the memory being an output memory;

transfer the first data and the address to a processor of a plurality of processors;

cause the first data to be processed by the processor to form processed first data;

store the processed first data in the memory at the location corresponding to the address;

receive second data;

selectively assign, to the second data, a same address as the address based on the first data and the second data being fragments of a same packet; and

selectively assign, to the second data, a different address than the address based on the first data and the second data not being fragments of the same packet,

the different address corresponding to a different location in the memory.

17. The computer-readable medium of claim 16, where the address is associated with the processor.

18. The computer-readable medium of claim 16, where the one or more instructions that cause the one or more processors to assign the address corresponding to the location in the memory include:

one or more instructions that cause the one or more processors to;

store the address in a second location in a second memory; and

reserve the location in the memory.

19. The computer-readable medium of claim 18, where the second location in the second memory, with respect to other locations in the second memory, corresponds to the location in the memory, with respect to other locations in the memory.

20. The computer-readable medium of claim 16, where the first data and the second data are not fragments of the same packet, and where the instructions further comprise:

one or more instructions that cause the one or more processors to;

receive the second data after receiving the first data;

assign, to the second data, the different address corresponding to a second location in the memory, the second location being after the location in the memory;

transfer the second data and the different address to a second processor of the plurality of processors;

cause the second data to be processed by the second processor to form second processed data; and

store the second processed data in the memory at the second location corresponding to the different address.