Solid-state imaging element having image signal overflow path

• US 9,179,081 B2
• Filed: 03/18/2014
• Issued: 11/03/2015
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ueno, Takahisa, Yonemoto, Kazuya, Suzuki, Ryoji, Shiono, Koichi
• Primary Examiner(s): MOE, AUNG SOE
• Application Number:
  US14/218,485
• Publication Number:
  US 20140198241A1
• Time in Patent Office: 595 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/441 by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Since the great number of elements constituting a unit pixel having an amplification function would hinder reduction of pixel size, unit pixel n,m arranged in a matrix form is comprised of a photodiode, a transfer switch for transferring charges stored in the photodiode, a floating diffusion for storing charges transferred by the transfer switch, a reset switch for resetting the floating diffusion, and an amplifying transistor for outputting a signal in accordance with the potential of the floating diffusion to a vertical signal line, and by affording vertical selection pulse φVn to the drain of the reset switch to control a reset potential thereof, pixels are selected in units of rows.

Claims

1. A solid state imaging device comprising:

a plurality of unit pixels, each of the unit pixels including

a photoelectric conversion element,

a transfer transistor associated with the photoelectric conversion element and a charge store element,

an amplifying transistor associated with the charge store element and a signal line, and

a reset transistor associated with the charge store element,

wherein a drain of the reset transistor is configured to receive a plurality of voltages from a selection line, and

wherein the plurality of voltages includes a first voltage and a second voltage, the first voltage being selected during a first situation and the second voltage being selected during a second situation.

2. The solid state imaging device according to claim 1, wherein:

the first situation is based on the pixel correspond to a selection state; and

the second situation is based on the pixel correspond a non-selection state.

3. The solid state imaging device according to claim 1, wherein the charge store element is a floating diffusion region.

4. The solid state imaging device according to claim 1, wherein the reset transistor is configured to reset the charge store element.

5. The solid state imaging device according to claim 1, wherein a gate of the amplifying transistor is electrically connected to the charge store element.

6. The solid state imaging device according to claim 1, wherein a gate of the reset transistor is electrically connected to a reset line.

7. The solid state imaging device according to claim 1, wherein the transfer transistor is configured to transfer a signal charge from the photoelectric conversion element to the charge store element.

8. The solid state imaging device according to claim 7, wherein the photoelectric conversion element is configured to convert incident light into the signal charge.

9. The solid state imaging device according to claim 1, wherein:

the charge store element is a floating diffusion region;

a gate of the amplifying transistor is electrically connected to the floating diffusion region;

a gate of the reset transistor is electrically connected to a reset control line;

a gate of the transfer transistor is electrically connected to a transfer control line;

the reset transistor is configured to reset the floating diffusion region; and

the transfer transistor is configured to transfer a signal charge from the photoelectric conversion element to the floating diffusion region.

10. The solid state imaging device according to claim 9, wherein:

the signal line extends along a first direction; and

the selection line, the reset control line, and the transfer control line extends along a second direction which is different with the first direction.

11. The solid state imaging device according to claim 9, wherein a negative potential is applied to the gate of the transfer transistor.

12. The solid state imaging device according to claim 11, wherein a drain terminal of the amplifying transistor is connected to a voltage line, the voltage line being different from the selection line.

13. An electronic apparatus comprising:

the solid state imaging device according to claim 9.

14. The solid state imaging device according to claim 1, wherein a source terminal of the amplifying transistor is directly connected to the signal line.

15. The solid state imaging device according to claim 1, further comprising a vertical scanning circuit and a horizontal scanning circuit.

16. The solid state imaging device according to claim 15, further comprising an output circuit is configured to output image signals supplied from the unit pixels.

17. The solid state imaging device according to claim 16, wherein the output circuit is configured to be controlled by the horizontal scanning circuit.

18. The solid state imaging device according to claim 1, wherein the reset transistor is a depression type transistor.

19. An electronic apparatus comprising:

the solid state imaging device according to claim 1.