Device and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer

• US 9,181,633 B2
• Filed: 10/15/2008
• Issued: 11/10/2015
• Est. Priority Date: 07/01/2005
• Status: Active Grant

• Current Assignee: Freiberger Compound Materials GMBH (Federmann House Limited)
• Original Assignee: Freiberger Compound Materials GMBH (Federmann House Limited)
• Inventors: Jurisch, Manfred, Eichler, Stefan, Bnger, Thomas, Weinert, Berndt, Brner, Frank
• Primary Examiner(s): SONG, MATTHEW J
• Application Number:
  US12/251,754
• Publication Number:
  US 20090104423A1
• Time in Patent Office: 2,582 Days
• Field of Search: 117/7, 117/84, 117/89, 117/92, 117/95, 117/97, 428/64, 428/156, 428/172, 428/219, 428/409, 428/688
• US Class Current: 1/1
• CPC Class Codes: C30B 11/00 Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method C30B13/00, C30B15/00, C30B17/00, C30B19/00 take precedence; under a protective fluid C30B27/00
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/42 Gallium arsenide
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: C30B 35/00 Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 21/67346 characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: Y10T 117/10 Apparatus
• CPC Class Codes: Y10T 428/21 Circular sheet or circular blank
• CPC Class Codes: Y10T 428/24479 including variation in thickness
• CPC Class Codes: Y10T 428/24612 Composite web or sheet
• CPC Class Codes: Y10T 428/31 Surface property or characteristic of web, sheet or block

Abstract

A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×10⁴ cm⁻² is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.

Claims

1. A GaAs semiconductor single crystal wafer having a diameter of ≧

100 mm and a dislocation density of about ≦

1×

10⁴ cm<sup>−

2</sup>,

wherein said GaAs semiconductor single crystal wafer is semi-insulating (SI) and has a mean EL2 concentration of at least 1.4×

10¹⁶ cm<sup>−

3</sup>,

wherein the surface of said GaAs semiconductor single crystal wafer has a number of light point defects (lpd), measured in an lpd size range of 0.3-2.0 μ

m, of smaller than about 0.3 cm<sup>−

2</sup>,

wherein said GaAs semiconductor single crystal wafer is derived from Vertical Gradient Freeze (VGF)- or Vertical Bridgman (VB)-produced GaAs single crystal, and

wherein a characteristic fracture strength, at which the wafer has a probability of failure of about 63.2% (Weibull characteristic strength σ

of test piece), is higher than about 1900 MPa.

2. A GaAs semiconductor single crystal wafer according to claim 1, being further defined by at least one of the following features:

a concentration of total impurities other than carbon and boron of about ≦

5×

10¹⁴ cm<sup>−

3</sup>, and

|Δ

[EL2⁰]/[EL2⁰]|≦

7.5%

and

σ

_mesos≦

6%.

3. A GaAs semiconductor single crystal wafer according to claim 1, produced by a process for heat treating, at an increased temperature, a wafer comprising, at least at a surface thereof, a III-V semiconductor material, the wafer having a diameter of ≧

100 mm, wherein the process comprises;

placing one or more wafers having a diameter of ≧

100 mm in an interior space of a heating furnace or container;

heating the wafer at an increased temperature, under a condition wherein a limited gas exchange is ensured between the surface of the wafer to be heat treated and the interior space c the heating furnace or container, such that precipitates of the V component are substantially reduced in size and/or density in a surface layer of the III-V semiconductor material-comprising surface of the wafer.

4. A GaAs semiconductor single crystal wafer according to claim 1, produced by a process for heat treating at an increased temperature a wafer comprising, at least at a surface thereof, a GaAs semiconductor material, wherein the process comprises:

providing a wafer comprising, at least at a surface thereof, the GaAs semiconductor material, the wafer having a diameter of ≧

100 mm,

heating the wafer at an increased temperature, under a condition that extracts As from a region of the GaAs-comprising surface, thereby substantially reducing density and/or size of As-precipitates in the surface region, the surface region being at least about 5 μ

m or more in thickness.

5. A GaAs semiconductor single crystal wafer according to claim 1, produced by a process for heat treating at an increased temperature a wafer comprising a III-V semiconductor material and having a diameter of ≧

100 mm, comprising;

after a step for purifying and etching, and before a step for edge-grinding, heating the wafer at an increased temperature in a heat treatment device that is free of quartz and that comprises at least one wafer support unit.