System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
First Claim
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1. An apparatus, comprising:
- a plurality of memories including NAND flash memory and random access memory;
a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and
a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory;
said DDR protocol being operable for allowing a single complete read or write operation in response to a single read or write command;
said apparatus configured for;
receiving, at the first circuit via the first bus, a first command for initiating a particular single complete read or write operation in connection with particular information;
after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories, utilizing the second circuit; and
receiving, at the first circuit via the first bus, a second command for completing the particular single complete read or write operation in connection with the particular information.
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Abstract
An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads.
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Citations
44 Claims
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1. An apparatus, comprising:
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a plurality of memories including NAND flash memory and random access memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said DDR protocol being operable for allowing a single complete read or write operation in response to a single read or write command; said apparatus configured for; receiving, at the first circuit via the first bus, a first command for initiating a particular single complete read or write operation in connection with particular information; after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories, utilizing the second circuit; and receiving, at the first circuit via the first bus, a second command for completing the particular single complete read or write operation in connection with the particular information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. An apparatus, comprising:
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a plurality of memories including NAND flash memory and random access memory; first circuitry configured to receive DDR signals and output SATA signals, the first circuitry configured for being communicatively coupled to a first bus for use with a DDR protocol; and second circuitry configured to receive the SATA signals and output NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory; said apparatus configured for; receiving, by the first circuitry via the first bus, a first command, for initiating a particular single complete read or write operation on particular information; after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories; receiving, by the first circuitry via the first bus, a second command; and after the receipt of the second command, sending, to at least one processor via the first bus, the particular information, for completing the particular single complete read or write operation on the particular information; said apparatus configured such that, despite the first bus being operable for allowing a single complete read or write operation after a single read or write command is received by the at least one processor, the particular single complete read or write operation requires both the first command and the second command to complete the particular single complete read or write operation on the particular information, to support the particular information that is in the one of the plurality of memories being made available in the another one of the plurality of memories.
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43. An apparatus, comprising:
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a plurality of memories including NAND flash memory and random access memory; first circuitry configured to receive DDR signals via a first bus;
the first circuitry further configured to output SATA signals; andsecond circuitry configured to receive the SATA signals via a second bus, the second circuitry further configured to output NAND flash signals via a third bus; said first bus being operable for communicating one read or write command that corresponds with one read or write operation; said apparatus configured for; receiving, by the first circuitry via the first bus, a first command for a particular read or write operation on particular information; after the receipt of the first command, writing the particular information that is in one of the plurality of memories to another one of the plurality of memories, utilizing the second circuitry; and receiving, by the first circuitry via the first bus, a second command for the particular read or write operation on the particular information.
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44. An apparatus, comprising:
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NAND flash memory means; random access memory means; first means for receiving DDR signals via a first bus using a DDR protocol; and second means for receiving SATA signals and outputting NAND flash signals; said DDR protocol being operable for allowing a single complete read operation in response to a single read command; said apparatus configured for; receiving, via the first bus, a first command for initiating a particular single complete read operation on particular information; after the receipt of the first command, making the particular information available in at least one of the NAND flash memory means or the random access memory means; and receiving, via the first bus, a second command for completing the particular single complete read operation on the particular information.
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Specification