Method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers

• US 9,182,992 B2
• Filed: 06/10/2013
• Issued: 11/10/2015
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Esencia Technologies Inc. (Larsen & Toubro Limited)
• Inventors: Guerrero, Miguel A
• Primary Examiner(s): Tseng, Cheng-Yuan
• Application Number:
  US13/914,323
• Publication Number:
  US 20130332704A1
• Time in Patent Office: 883 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers allows for either decreased register spillage or decreased area and power consumption of a microprocessor. The microprocessor takes advantage of register bypass logic to write short-lived values to virtual registers, which are discarded instead of being written to the register bank, thus reducing register pressure by avoiding short-lived values being written to the register bank.

Claims

1. A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers, the method comprises the steps of:

providing a microprocessor, wherein a periodic clock cycle coordinates commands executed by the microprocessor;

providing a register bank, wherein the register bank comprises a number of physical registers (R);

providing a specific pipeline datapath and a plurality of optional additional pipeline datapaths within the microprocessor,

wherein N is the total number of pipeline datapaths;

wherein the specific pipeline datapath and the plurality of optional additional pipeline datapaths each comprise a plurality of pipeline stages;

wherein the plurality of pipeline stages includes an execution stage and a writeback stage;

wherein the execution stage occurs before the writeback stage;

wherein the specific pipeline datapath and the plurality of optional additional pipeline datapaths each comprise a number of pipeline registers (P) between the execution stage and the writeback stage;

processing a source instruction with the specific pipeline datapath;

processing a corresponding instruction with an arbitrary pipeline datapath, wherein the arbitrary pipeline datapath is either the specific pipeline datapath or one of the plurality of optional additional pipeline datapaths;

sequentially executing the plurality of pipeline stages for both the specific pipeline datapath and the plurality of optional additional pipeline datapaths;

producing an output value with the specific pipeline datapath;

storing the output value within the register bank, if the output value is not used as an input value for the corresponding instruction within P clock cycles;

storing the output value within the register bank,

if the output value is used as an input value for the corresponding instruction within P clock cycles; and

if the output value is used as a subsequent input value for a future arbitrary subsequent instruction,

wherein the future arbitrary subsequent instruction uses the output value as a subsequent input value after P clock cycles;

storing the output value within a Pipeline Virtual Register (PVR),

if the output value is used as an input value for the corresponding instruction within P clock cycles, and

if the output value is not used as an input value for any subsequent instructions.

2. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, the method comprises the steps of:

providing register bypass logic, wherein the register bypass logic is able to access the specific pipeline datapath and the plurality of optional additional pipeline datapaths;

analyzing the input value with the register bypass logic to determine whether the input value was produced P or fewer clock cycles prior to the execution stage of the arbitrary pipeline datapath;

retrieving the input value from the register bank, if the input value was not produced P or fewer clock cycles prior to the execution stage of the arbitrary pipeline datapath; and

retrieving the input value from the specific pipeline datapath, if the input value was produced P or fewer clock cycles prior to the execution stage of the plurality of optional additional pipeline datapaths.

3. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the corresponding instruction is initialized at least one clock cycle after the source instruction is initialized by the microprocessor.

4. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the output value is killed after the corresponding instruction.

5. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein each of the R physical registers has a register index value less than or equal to R.

6. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 5, wherein the output value is assigned a register index value greater than R.

7. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the output value is produced by the execution stage of the specific pipeline datapath.

8. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein P−

1 is the number of pipeline stages between the execution stage and the writeback stage.

9. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the output value is discarded during the writeback stage of the specific pipeline datapath.

10. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the microprocessor is a configurable microprocessor with vector capabilities.

11. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, the method comprises the steps of:

providing a total number of accessible registers (A), wherein A is initially equal to R; and

increasing A from R to the sum of R and P*N in order to minimize spilling of live values from the register bank onto local memory by using P*N PVRs,

wherein short lived values are written to the P*N PVRs;

wherein the short lived values written to the P*N PVRs are discarded during the writeback stage.

12. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, the method comprises the steps of:

providing a total number of accessible registers (A), wherein A is initially equal to R;

decreasing R to a smaller number of physical registers (S), wherein A is similarly decreased from R to S; and

increasing A from S to the sum of S and P*N in order to reduce physical area, write-back dynamic power consumption and power leakage of the microprocessor,

wherein short lived values are written to an additional P*N PVRs;

wherein the short lived values written to the additional P*N PVRs are discarded during the writeback stage.

13. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein the microprocessor implements register bypass logic to allocate short-lived values to a plurality of PVRs.

14. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, the method comprises the steps of:

providing a plurality of PVRs, wherein the plurality of PVRs contains live values;

copying the live values from the plurality of PVRs to memory, if an asynchronous exception is encountered by the microprocessor;

executing an exception handling routine to correct the asynchronous exception, if the asynchronous exception is encountered by the microprocessor; and

restoring the live values from memory to the plurality of PVRs after the microprocessor executes the exception handling routine.

15. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1, wherein a compiler allocates the PVR for a short lived value only in regions of code where the compiler can ensure that no exceptions will be encountered by the microprocessor.

16. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 15, wherein no instructions in the specific regions of code can generate a synchronous exception and either the microprocessor is not configured to support exceptions or exceptions are disabled.

17. The method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers as claimed in claim 1,

providing a register bypass network, wherein the register bypass network comprises a plurality of PVRs;

providing a first register cluster and a second register cluster,

wherein the first register cluster and the second register cluster cannot directly communicate with each other;

transferring a live value from the first register cluster to an arbitrary PVR from the plurality of PVRs; and

transferring the live value from the arbitrary PVR to the second register cluster.