Error detection and correction of one-time programmable elements

• US 9,183,082 B2
• Filed: 01/29/2013
• Issued: 11/10/2015
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jung Pill, Kim, Taehyun, Kim, Sungryul
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US13/752,419
• Publication Number:
  US 20140215294A1
• Time in Patent Office: 1,015 Days
• Field of Search: 714/819
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 17/02 using magnetic or inductive elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/027 in fuses

Abstract

A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

Claims

1. A circuit comprising:

a first one-time programmable (OTP) element;

a second OTP element;

error detection circuitry coupled to receive a first representation of data from the first OTP element and to receive a second representation of the data from the second OTP element; and

output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on the second representation of the data from the second OTP element, wherein the output of the error detection circuitry includes a first flag indicating whether any uncorrectable errors are detected in the first representation of the data and a second flag indicating whether any uncorrectable errors are detected in the second representation of the data, and wherein the output circuitry generates a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted.

2. The circuit of claim 1, wherein the first OTP element is included in a first set of magnetic tunnel junction (MTJ) OTP elements.

3. The circuit of claim 1, wherein the second OTP element is included in a second set of magnetic tunnel junction (MTJ) OTP elements.

4. The circuit of claim 1, wherein the error detection circuitry comprises an error correction code (ECC) decoder.

5. The circuit of claim 4, wherein the ECC decoder comprises a single error correction (SEC) and double error detection (DED) (SEC-DEC) decoder.

6. The circuit of claim 1, wherein the error detection circuitry comprises a cyclic redundancy check (CRC) decoder.

7. The circuit of claim 1, wherein the output circuitry includes a multiplexer configured to select an error correction code (ECC) data output corresponding to a particular representation of the data in response to the selection signal, wherein the output circuitry is further configured to generate an error signal when the first flag and the second flag are asserted.

8. The circuit of claim 1, wherein the output circuitry is integrated into at least one semiconductor die.

9. The circuit of claim 1, wherein the output circuitry is integrated in a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a computer, or a combination thereof.

10. A method comprising:

generating a first flag based on a first representation of data stored in a first one-time programmable (OTP) element, wherein the first flag indicates whether the first representation of the data includes any uncorrectable errors;

generating a second flag based on a second representation of the data stored in a second OTP element, wherein the second flag indicates whether the second representation of the data includes any uncorrectable errors;

responsive to the first flag and the second flag, generating a read output based on the first representation of the data or the second representation of the data and

generating a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted.

11. The method of claim 10, further comprising:

performing a first error detection operation on the first representation of the data to generate the first flag; and

performing a second error detection operation on the second representation of the data to generate the second flag.

12. The method of claim 10, further comprising performing an error correction operation with respect to a particular representation of the data in response to determining that the particular representation of the data includes a correctable error.

13. The method of claim 10, wherein when the first flag indicates that the first representation of the data includes no uncorrectable errors and the second flag indicates that the second representation of the data includes at least one uncorrectable error, the read output is generated based on the first representation of the data.

14. The method of claim 10, wherein when the second flag indicates that the second representation of the data includes no uncorrectable errors and the first flag indicates that the first representation of the data includes at least one uncorrectable error, the read output is generated based on the second representation of the data.

15. The method of claim 10, wherein the first flag, the second flag, and the read output are generated at circuitry integrated into an electronic device.

16. An apparatus comprising:

a first one-time programmable (OTP) element;

a second OTP element;

means for receiving a first representation of data from the first OTP element and a second representation of the data from the second OTP element; and

means, responsive to an output of the means for receiving, for outputting an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element, wherein the means for outputting includes a first flat indicating whether an uncorrectable errors are detected in the first representation of the data and a second flag indicating whether any uncorrectable errors are detected in the second representation of the data, and wherein the means for outputting generates a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted.

17. The apparatus of claim 16, wherein the first OTP element is included in a first set of magnetic tunnel junction (MTJ) OTP elements and wherein the second OTP element is included in a second set of MTJ OTP elements.

18. The apparatus of claim 16, wherein the means for receiving comprises error detection circuitry coupled to the first OTP element and to the second OTP element.

19. The apparatus of claim 18, wherein the means for outputting comprises a multiplexer configured to select an error correction code (ECC) data output corresponding to a particular representation of the data in response to the error detection circuitry indicating that no uncorrectable errors are detected in the particular representation of the data.

20. The apparatus of claim 16, wherein the means for receiving and the means for outputting are integrated in a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a computer, or a combination thereof.

21. A method comprising:

a step for generating a first flag based on a first representation of data stored in a first one-time programmable (OTP) element, wherein the first flag indicates whether the first representation of the data includes any uncorrectable errors;

a step for generating a second flag based on a second representation of the data stored in a second OTP element, wherein the second flag indicates whether the second representation of the data includes any uncorrectable errors;

a step for, responsive to the first flag and the second flag, generating a read output based on the first representation of the data or the second representation of the data, and

a step for generating a selection signal having a first value when the first flag is de-asserted asserted and having a second value when the first flag is asserted and the second flag is de-asserted.

22. The method of claim 21, wherein the step for generating the first flag, the step for generating the second flag, and the step for generating the read output are performed at circuitry integrated into an electronic device.

23. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to:

cause generation of a first flag based on a first representation of data stored in a first one-time programmable (OTP) element, wherein the first flag indicates whether the first representation of the data includes any uncorrectable errors;

cause generation of a second flag based on a second representation of the data stored in a second OTP element, wherein the second flag indicates whether the second representation of the data includes any uncorrectable errors;

responsive to the first flag and the second flag, cause generation of a read output based on the first representation of the data or the second representation of the data; and

cause generation of a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted.

24. The non-transitory computer-readable medium of claim 23, wherein the processor is integrated into a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a computer, or a combination thereof.

25. A method comprising:

receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising;

a first one-time programmable (OTP) element;

a second OTP element;

error detection circuitry coupled to receive a first representation of data from the first OTP element and to receive a second representation of the data from the second OTP element; and

output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on the second representation of the data from the second OTP element, wherein the output of the error detection circuitry includes a first flag indicating whether any uncorrectable errors are detected in the first representation of the data and a second flag indicating whether any uncorrectable errors are detected in the second representation of the data, and wherein the output circuitry generates a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted;

transforming the design information to comply with a file format; and

generating a data file including the transformed design information.

26. The method of claim 25, wherein the data file comprises a GDSII format.

27. The method of claim 25, wherein the data file comprises a GERBER format.