Memory control device, memory control method, data processing device, and image processing system

• US 9,183,131 B2
• Filed: 11/03/2014
• Issued: 11/10/2015
• Est. Priority Date: 10/18/2011
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ninomiya, Yasuyuki
• Primary Examiner(s): SCHNEE, HAL W
• Application Number:
  US14/531,787
• Publication Number:
  US 20150058581A1
• Time in Patent Office: 372 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 2212/15 Use in a specific computing environment
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

Claims

1. A data processing device, comprising:

a Central Processing Unit (CPU);

a memory;

a SIMD (Single Instruction Multiple Data) Processor; and

a bus through which the CPU, the memory and the SIMD processor are coupled each other;

wherein the SIMD Processor comprises;

a data Processing unit having a plurality of processing elements (PEs); and

a control processor (CP) that controls the PEs;

wherein the control processor includes;

an absolute address register that stores an absolute address serving as a common reference value in a given data transfer period therein;

a first differential address register that stores a plurality of first differential addresses therein, each of the first differential addresses indicating a difference between a read address and the absolute address;

a first pointer register that designates the plurality of first differential addresses in a given order;

a memory address generator circuit that combines any of the first differential addresses selected by the first pointer register with the absolute address to generate a memory address; and

a data transfer circuit that inputs the memory address generated by the memory address generator circuit to the memory, and reads and transfers data from the memory address.

2. An image processing system, comprising:

the data processing apparatus of claim 1;

an image pickup device that picks up an image and stores the image in the memory;

wherein

the data processing device reads image data temporarily stored in the memory to conduct given data processing; and

an image display device that displays the image data that has been subjected to the given data processing by the data processing device.

3. The data processing device according to claim 1, wherein the control processor further includes:

a second differential address register that stores a plurality of second differential addresses therein, each of the second differential addresses indicating a difference between a read address and the absolute address;

a second pointer register that designates the plurality of second differential addresses in a second given order; and

, wherein

the memory address generator circuit combines any first differential address and any second differential address selected by the first and second pointer registers with the absolute address to generate a memory address.

4. An image processing system, comprising:

the data processing apparatus of claim 3;

an image pickup device that picks up an image and stores the image in the memory;

wherein

the data processing device reads image data temporarily stored in the memory to conduct given data processing; and

an image display device that displays the image data that has been subject to the given data processing by the data processing device.

5. A semiconductor integrated circuit, comprising:

a Central Processing Unit (CPU);

a memory;

a SIMD (Single Instruction Multiple Data) Processor; and

a bus through which the CPU, the memory and the SIMD processor are coupled each other;

wherein the SIMD Processor comprises;

a data Processing unit having a plurality of processing elements (PEs); and

a control processor (CP) that controls the PEs;

wherein the control processor includes;

an absolute address register that stores an absolute address serving as a common reference value in a given data transfer period therein;

a first differential address register that stores a plurality of first differential addresses therein, each of the first differential addresses indicating a difference between a read address and the absolute address;

a first pointer register that designates the plurality of first differential addresses in a given order;

a memory address generator circuit that combines any of the first differential addresses selected by the first pointer register with the absolute address to generate a memory address; and

a data transfer circuit that inputs the memory address generated by the memory address generator circuit to the memory, and reads and transfers data from the memory address.

6. The semiconductor integrated circuit according to claim 5, wherein the control processor further includes:

a second differential address register that stores a plurality of second differential addresses therein, each of the second differential addresses indicating a difference between a read address and the absolute address;

a second pointer register that designates the plurality of second differential addresses in a second given order; and

, wherein

the memory address generator circuit combines any first differential address and any second differential address selected by the first and second pointer registers with the absolute address to generate a memory address.