Power gating a portion of a cache memory
First Claim
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1. A processor comprising:
- a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first level cache and a second level cache, wherein each of the first level cache and the second level cache is physically private to the tile; and
a controller coupled to the plurality of tiles, the controller including a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a first tile and to cause the second level cache of the first tile to be independently power gated when a miss rate of the first level cache is less than a first threshold, based at least in part on the utilization information.
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Abstract
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
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Citations
17 Claims
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1. A processor comprising:
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a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first level cache and a second level cache, wherein each of the first level cache and the second level cache is physically private to the tile; and a controller coupled to the plurality of tiles, the controller including a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a first tile and to cause the second level cache of the first tile to be independently power gated when a miss rate of the first level cache is less than a first threshold, based at least in part on the utilization information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A machine-readable non-transitory medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
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determining an estimated idle duration for a core of a multicore processor, the core associated with a private cache hierarchy including a first level cache, a mid-level cache (MLC) and a last level cache (LLC); determining a time value for a break even condition for a first workload and storing the time value in a storage of the multicore processor, wherein the break even condition is a minimum amount of time for the LLC to be in a low power state; and power gating the LLC when the estimated idle duration is greater than the time value, while at least one other core of the multicore processor associated with another private cache hierarchy remains in an active state. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A system comprising:
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a multicore processor having a plurality of tiles, each tile including a core and a tile cache hierarchy, the tile cache hierarchy including a first level cache, a mid-level cache (MLC) and a last level cache (LLC), wherein each of the first level cache, the MLC and the LLC are private to the tile, and a cache power control logic to receive performance metric information regarding the tile cache hierarchy of a first tile of the plurality of tiles and to cause the LLC of the first tile to be power gated when a miss rate of the MLC is less than a first threshold based at least in part on the performance metric information, while the core, the first level cache and the MLC of the first tile remain in an active state; and a dynamic random access memory (DRAM) coupled to the multicore processor. - View Dependent Claims (16, 17)
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Specification