Pattern selection for full-chip source and mask optimization

• US 9,183,324 B2
• Filed: 05/07/2013
• Issued: 11/10/2015
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Liu, Hua-Yu
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US13/888,816
• Publication Number:
  US 20130311958A1
• Time in Patent Office: 917 Days
• Field of Search: 716/51, 716/53, 716/54, 716/55, 716/56, 430/5, 430/22, 355/46
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Claims

1. A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate, the method comprising:

selecting a subset of patterns from the portion of the design layout;

co-optimizing an illumination source of the lithographic process and only the selected subset of patterns to improve the lithographic process; and

verifying that a resulting configuration of the co-optimized illumination source will achieve a specified imaging performance for a larger set of patterns comprising the portion of the design layout and not only the selected subset of patterns when the portion of the design layout is imaged onto the substrate by the lithographic process including the configured co-optimized illumination source,

wherein one or more of the above steps are performed by the computer.

2. The method of claim 1, wherein the step of verifying that the specified imaging performance will be achieved includes determining whether the portion of the design layout will print across a desired process window for the lithographic process.

3. The method of claim 1, wherein the portion of the design layout comprises a full chip.

4. The method of claim 1, wherein selecting the subset of patterns is based on calculating diffraction order distributions for the portion of the design layout.

5. The method of claim 4, wherein calculating the diffraction order distributions for the portion of the design layout comprises:

determining magnitude and phase of diffraction orders which form an image in an image plane that optimizes image log slope at fragmentation points identified within the portion of the design layout.

6. The method of claim 1, wherein the selected subset of patterns is updated in an iterative manner to better represent the entire portion of the design layout.

7. The method of claim 6, wherein the selected subset of patterns is updated for an iteration by adding hotspots extracted by simulating the lithographic process using a configuration of the illumination source and the portion of the design layout in a previous iteration.

8. The method of claim 6, wherein the lithographic process is verified for manufacturability for at least one of the iterations.

9. The method of claim 8, wherein the verification for manufacturability includes:

performing an aerial image simulation of the selected patterns and the optimized source for a particular iteration.

10. The method of claim 9, wherein the verification for manufacturability further includes:

verifying that the selected patterns print across a desired process window for the illumination source configuration for the particular iteration.

11. The method of claim 10, wherein the desired process window comprises a specified exposure latitude and depth of focus.

12. A computer program product comprising a non-transitory computer readable medium having instructions thereon, the instructions, when executed by a computer, implements a method for improving a lithographic process for imaging a portion of a design layout onto a substrate, by performing the steps of:

selecting a subset of patterns from the portion of the design layout;

co-optimizing an illumination source of the lithographic process and only the selected subset of patterns to improve the lithographic process; and

verifying that a resulting configuration of the co-optimized illumination source achieves a specified imaging performance for a larger set of patterns comprising the portion of the design layout and not only the selected subset of patterns when the portion of the design layout is imaged onto the substrate by the lithographic process including the configured illumination source.

13. The computer program product of claim 12, wherein the step of verifying that the specified imaging performance will be achieved includes determining whether the portion of the design layout will print across a desired process window for the lithographic process.

14. The computer program product of claim 12, wherein the portion of the design layout comprises a full chip.

15. The computer program product of claim 12, wherein selecting the subset of patterns is based on calculating diffraction order distributions for the portion of the design layout.

16. The computer program product of claim 12, wherein the selected subset of patterns is updated in an iterative manner to better represent the entire portion of the design layout.

17. The computer program product of claim 16, wherein the selected subset of patterns is updated for an iteration by adding hotspots extracted by simulating the lithographic process using a configuration of the illumination source and the portion of the design layout in a previous iteration.

18. The computer program product of claim 16, wherein the lithographic process is verified for manufacturability for at least one of the iterations.

19. The computer program product of claim 18, wherein the verification for manufacturability includes:

performing an aerial image simulation of the selected patterns and the optimized source for a particular iteration.

20. The computer program product of claim 19, wherein the verification for manufacturability further includes:

verifying that the selected patterns print across a desired process window for the illumination source configuration for the particular iteration.