Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs

• US 9,183,343 B1
• Filed: 12/04/2012
• Issued: 11/10/2015
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey S., Ananthram, Supriya, Mankad, Viral
• Primary Examiner(s): Levin, Naum
• Application Number:
  US13/705,164
• Time in Patent Office: 1,071 Days
• Field of Search: 716/126, 716129-130, 716/132, 716/136
• US Class Current: 1/1
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of interest may be projected onto a boundary of the region of interest, to determine the valid interval(s) on along the boundary. The valid intervals may then be used by a router to implement the multi-strands of interconnects. The router also considers the physical, electrical, and manufacturing requirement(s) in implementing the multi-strands of interconnects.

Claims

1. A computer implemented method for implementing current carrying interconnects in an electronic design, comprising:

using at least one processor or at least one processor core of an electronic design automation (EDA) system to perform a process, the process comprising;

identifying a first pin and a second pin of a plurality of pins in the electronic design;

determining or identifying an available area for interconnecting the first pin and the second pin by analyzing a region of interest; and

implementing a first interconnect for the first pin based at least in part upon a first strand number for the first interconnect used to connect the first pin and the second pin and an electric current requirement, rather than upon changing a width of the first interconnect for the first pin.

2. The computer implemented method of claim 1, wherein the act of implementing the first interconnect for the first pin is based further at least in part upon a routing topology, one or more requirements, or a second strand number.

3. The computer implemented method of claim 2, the process further comprising:

determining or identifying the routing topology based at least in part upon a characteristic of the first pin and the second pin of the plurality of pins.

4. The computer implemented method of claim 2, the one or more requirements comprising a physical requirement, an electrical requirement, a performance requirement, a manufacturing requirement, or a functionality of the first interconnect in the electronic design.

5. The computer implemented method of claim 3, the characteristic comprises a first position of the first pin and a second position of the second pin, a first orientation of the first pin and a second orientation of the second pin, or relative orientation of the first pin and the second pin.

6. The computer implemented method of claim 1, wherein the act of implementing the first interconnect for the first pin is based further at least in part upon an area-based search strategy.

7. The computer implemented method of claim 1, the process further comprising:

clustering multiple pins of the plurality of pins to form a single pin.

8. The computer implemented method of claim 7, wherein the act of clustering the multiple pins comprises:

identifying a threshold requirement of proximity between two adjacent pins of the multiple pins;

identifying the multiple pins based at least in part upon the threshold requirement of proximity; and

clustering the multiple pins into the single pin based at least in part upon an area match or a boundary match.

9. The computer implemented method of claim 1, the process further comprising:

strapping the first interconnect for the first pin and a second interconnect for the second pin at an intersection of the first interconnect and the second interconnect.

10. The computer implemented method of claim 1, the process further comprising:

identifying a blockage in the region of interest; and

determining whether the blockage can be modified.

11. The computer implemented method of claim 1, the process further comprising:

determining or identifying one or more first valid intervals for the region of interest.

12. The computer implemented method of claim 11, the act of determining or identifying the one or more first valid intervals comprising:

identifying a first boundary segment of the region of interest;

projecting one or more geometries of the electronic design onto the first boundary to form one or more projected geometries along the first boundary;

fragmenting the first boundary based at least in part upon the one or more projected geometries; and

identifying the one or more first valid intervals in the region of interest based at least in part upon a fragmentation result of the first boundary.

13. The computer implemented method of claim 11, the act of determining or identifying the one or more first valid intervals comprising:

generating a first set of spacetiles by at least performing a spacetile punch for the region of interest;

identifying a first boundary of the region of interest based at least in part upon the first pin or the second pin; and

identifying or determining the one or more first valid intervals with respect to the first boundary based at least in part upon analyzing at least some of the first set of spacetiles.

14. The computer implemented method of claim 13, the act of determining or identifying the one or more first valid intervals further comprising:

partitioning a spacetile of the first set of spacetiles into multiple finer spacetiles.

15. The computer implemented method of claim 13, the act of determining or identifying the one or more first valid intervals further comprising:

creating one or more area probes by using at least some of the first set of spacetiles.

16. The computer implemented method of claim 1, wherein the act of implementing the first interconnect comprises:

performing an area-based search using at least one spacetile of a first set of spacetiles to identify a first routing solution from the first pin; and

implementing the first interconnect for the first pin by using at least the first routing solution.

17. The computer implemented method of claim 16, wherein the process further comprises:

identifying a second strand number for the second pin;

determining whether the first set of spacetiles is to be used to implement a second interconnect for the second pin;

generating a second set of spacetiles by at least performing a spacetile punch for the region of interest where the first set of spacetiles is determined not to be used to implement the second interconnect for the second pin;

performing the area-based search by using at least the first set of spacetiles or the second set of spacetiles to generate a second routing solution for the second pin; and

implementing the second interconnect for the second pin by using at least the second routing solution.

18. The computer implemented method of claim 16, wherein the process further comprises:

performing the area-based search by using at least the first set of spacetiles or a second set of spacetiles to generate a bridging routing solution for the second pin;

implementing a third interconnect to bridge the first interconnect and a second interconnect by using at least the bridging routing solution;

strapping the first interconnect and the third interconnect at a first intersection of the first interconnect and the third interconnect; and

strapping the second interconnect and the third interconnect at a second intersection of the second interconnect and the third interconnect.

19. A system for implementing high current carrying interconnects in an electronic design, comprising:

at least one processor or at least one processor core of an electronic design automation (EDA) system that is at least to;

identify a first pin and a second pin of a plurality of pins in the electronic design;

determine or identify an available area for interconnecting the first pin and the second pin by analyzing a region of interest; and

implement a first interconnect for the first pin based at least in part upon a first strand number for the first interconnect used to connect the first pin and the second pin and an electric current requirement, rather than upon changing a width of the first interconnect for the first pin.

20. The system of claim 19, wherein the at least one processor or at least one processor core is further to:

cluster multiple pins of the plurality of pins to form a single pin.

21. The system of claim 20, wherein the at least one processor or at least one processor core is further to:

determine or identify a routing topology based at least in part upon a characteristic of the first pin and the second pin of the plurality of pins.

22. The system of claim 19, wherein the at least one processor or at least one processor core is further to:

strap the first interconnect for the first pin and a second interconnect for the second pin at an intersection of the first interconnect and the second interconnect.

23. The system of claim 19, wherein the at least one processor or at least one processor core is further to:

identify a blockage in the region of interest; and

determine whether the blockage can be modified.

24. The system of claim 20, wherein the at least one processor or the at least one processor core that is to cluster the multiple pins is further to:

identify a threshold requirement of proximity between two adjacent pins of the multiple pins;

identify the multiple pins based at least in part upon the threshold requirement of proximity; and

cluster the multiple pins into the single pin based at least in part upon an area match or a boundary match.

25. The system of claim 19, wherein the at least one processor or at least one processor core is further to:

determine or identify one or more first valid intervals for the region of interest.

26. The system of claim 25, wherein the at least one processor or at least one process core is further to:

generate a first set of spacetiles by at least performing a spacetile punch for the region of interest;

identify a first boundary of the region of interest based at least in part upon the first pin or the second pin; and

identify or determine the one or more first valid intervals with respect to the first boundary based at least in part upon analyzing at least some of the first set of spacetiles.

27. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing high current carrying interconnects in an electronic design, the method comprising:

using the at least one processor or the at least one processor core of an electronic design automation (EDA) system to perform a process, the process comprising;

identifying a first pin and a second pin of a plurality of pins in the electronic design;

determining or identifying an available area for interconnecting the first pin and the second pin by analyzing a region of interest; and

implementing a first interconnect for the first pin based at least in part upon a first strand number for the first interconnect used to connect the first pin and the second pin and an electric current requirement, rather than upon changing a width of the first interconnect for the first pin.

28. The article of manufacture of claim 27, wherein the act of implementing the first interconnect comprises:

performing an area-based search using at least one spacetile of a first set of spacetiles to identify a first routing solution from the first pin; and

implementing the first interconnect for the first pin by using at least the first routing solution.

29. The article of manufacture of claim 28, wherein the process further comprises:

identifying a second strand number for the second pin;

determining whether the first set of spacetiles is to be used to implement a second interconnect for the second pin;

generating a second set of spacetiles by at least performing a spacetile punch for the region of interest where the first set of spacetiles is determined not to be used to implement the second interconnect for the second pin;

performing the area-based search by using at least the first set of spacetiles or the second set of spacetiles to generate a second routing solution for the second pin; and

implementing the second interconnect for the second pin by using at least the second routing solution.