High capacity memory system using standard controller component
First Claim
Patent Images
1. A memory module comprising:
- a plurality of device sites;
a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links;
at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites;
nine DQ buffer components coupled to the at least eighteen DRAM devices, each of the nine DQ buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine DQ buffer components includes the DQ buffer component; and
a command and address (CA) buffer component coupled to the at least eighteen DRAM devices.
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Abstract
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
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Citations
27 Claims
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1. A memory module comprising:
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a plurality of device sites; a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links; at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites; nine DQ buffer components coupled to the at least eighteen DRAM devices, each of the nine DQ buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine DQ buffer components includes the DQ buffer component; and a command and address (CA) buffer component coupled to the at least eighteen DRAM devices. - View Dependent Claims (2, 3, 5, 6, 7, 8, 14)
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4. A memory module comprising:
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a plurality of device sites; a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links; wherein the DQ buffer component comprises; two primary ports to couple to two of the multi-drop data-links in the first mode and to couple to two of the point-to-point data-links in the second mode; two secondary ports coupled to two of the plurality of device sites; a first bi-directional path between a first primary port of the two primary ports and a first secondary port of the two secondary ports; a second bi-directional path between a second primary port of the two primary ports and a second secondary port of the two secondary ports; and a third bi-directional path between the first primary port and the second secondary port. - View Dependent Claims (19, 20, 21, 22, 23)
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9. A memory module comprising:
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a plurality of device sites; and a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links; wherein the DQ buffer component further comprises; a first multiplexer comprising two inputs coupled to two primary ports and an output coupled to a second secondary port of two secondary ports; a second multiplexer comprising two inputs coupled to the two primary ports and an output coupled to a first secondary port of the two secondary ports; a third multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a first primary port of the two primary ports; and a fourth multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a second primary port of the two primary ports. - View Dependent Claims (10, 11, 12, 13, 24, 25, 26, 27)
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15. A printed circuit board (PCB) comprising:
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a plurality of pins; a plurality of memory devices; a command and address (CA) buffer component coupled to the plurality of memory devices; and a plurality of data (DQ) buffer components coupled to the plurality of memory devices, wherein a first DQ buffer component comprises; a plurality of primary ports coupled to the plurality of pins; a plurality of secondary ports coupled to the plurality of memory devices; and a plurality of bi-directional paths between the plurality of primary ports and the plurality of secondary ports, wherein the first DQ buffer component is programmed to operate the plurality of bi-directional paths in a first configuration when the PCB is inserted onto a first type of memory channel with multi-drop data-links and in a second configuration when the PCB is inserted onto a second type of memory channel with point-to-point data-links; wherein the plurality of bi-directional paths comprises; a first bi-directional path between a first primary port and a first secondary port; a second bi-directional path between a second primary port and a second secondary port; and a third bi-directional path between the first primary port and the second secondary port. - View Dependent Claims (16, 17, 18)
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Specification