Resistive memory device and method of operating the same

• US 9,183,932 B1
• Filed: 04/14/2015
• Issued: 11/10/2015
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Hyo-Jin, Lee, Yeong-Taek, Byeon, Dae-Seok, Lee, Yong-Kyu, Park, Hyun-Kook
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/685,671
• Time in Patent Office: 210 Days
• Field of Search: 365/46, 365/94, 365/100, 365/129, 365/148, 365/158, 365/163, 257 2- 5, 257/9, 257/295, 257/310, 257/E21.35, 438/95, 438/96, 438/135, 438/166, 438/240, 438/365, 438/482, 438/486, 438/597, 438/785
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode

Abstract

A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.

Claims

1. A method of operating a resistive memory device comprising a plurality of memory cells arranged in regions where a plurality of first signal lines and a plurality of second signal lines cross each other, the method comprising:

applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the plurality of memory cells;

applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line;

floating the unselected first signal lines; and

applying a third voltage that is higher than the first voltage to the selected first signal line.

2. The method of claim 1, wherein, when the third voltage is applied to the selected first signal line, a voltage level of the second line from among the unselected first signal lines changes from the second voltage to the first voltage.

3. The method of claim 1, wherein a voltage difference between the first voltage and the second voltage is determined based on a voltage difference between the first voltage and the third voltage.

4. The method of claim 1, wherein a voltage difference between the first voltage and the second voltage is set according to a kind of operation performed by the memory device.

5. The method of claim 1, wherein the third voltage is one of a reset writing voltage, a set writing voltage, and a reading voltage.

6. The method of claim 1, wherein floating the unselected first signal lines comprises:

floating the first line after applying the first voltage to the first line; and

floating the second line after applying the second voltage to the second line.

7. The method of claim 1, wherein a time period of applying the first voltage at least partially overlaps with a time period of applying the second voltage.

8. The method of claim 1, further comprising:

applying a fourth voltage that is equal to or higher than the first voltage to a first line, from among unselected second signal lines that are connected to the unselected memory cells, that is not adjacent to a selected second signal line connected to the selected memory cell;

applying a fifth voltage that is higher than the fourth voltage to a second line, from among the unselected second signal lines, that is adjacent to the selected second signal line;

floating the unselected second signal lines; and

applying a sixth voltage that is lower than the fourth voltage to the selected second signal line.

9. The method of claim 8, wherein the sixth voltage is substantially the same as a ground voltage.

10. The method of claim 1, wherein the resistive memory device comprises a plurality of memory layers stacked in a first direction,

wherein each of the plurality of memory layers comprises the plurality of memory cells arranged between the plurality of first signal lines arranged in a second direction that is perpendicular to the first direction and the plurality of second signal lines arranged in a third direction that is perpendicular to the first and second directions, and

wherein the second line from among the unselected first signal lines comprises at least one unselected first signal line adjacent to the selected first signal line in the first and second directions.

11. The method of claim 10, wherein each of the plurality of memory layers shares the first signal lines or the second signal lines with other adjacent memory layers.

12. A method of operating a resistive memory device comprising a plurality of memory cells, the method comprising:

applying a first voltage to an unselected signal line that is not adjacent to a selected signal line;

applying a second voltage having a different voltage level from a voltage level of the first voltage to a unselected signal line that is adjacent to the selected signal line; and

applying a third voltage having a different voltage level from the voltage levels of the first voltage and the second voltage, respectively, to the selected signal line,

wherein a voltage difference between the first voltage and the second voltage varies depending on an operation performed by the resistive memory device.

13. The method of claim 12, wherein a voltage difference between the first voltage and the second voltage is less than a voltage difference between the first voltage and the third voltage.

14. The method of claim 12, wherein the third voltage is one of a set writing voltage, a reset writing voltage, and a reading voltage, and the second voltage is lower than the first voltage.

15. The method of claim 12, wherein the third voltage is substantially the same as a ground voltage and the second voltage is higher than the first voltage.

16. A resistive memory device, comprising:

a memory cell array comprising a plurality of memory cells arranged in regions where a plurality of first signal lines and a plurality of second signal lines cross each other;

a voltage generator configured to generate a first voltage, a second voltage different from the first voltage, and a third voltage different from the first and second voltages; and

control logic configured to select a memory cell from among the plurality of memory cells, the selected memory cell being connected to a selected first signal line and a selected second signal line;

to apply the first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to the selected first signal line;

to apply the second voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; and

to apply the third voltage to the selected first signal line as the first and second lines are floated.

17. The resistive memory device of claim 16, wherein the third voltage is higher than the first voltage, and the second voltage is lower than the first voltage for minimizing leakage current flowing in an unselected memory cell connected to the second line.

18. The resistive memory device of claim 16, wherein the third voltage is lower than the first voltage, and the second voltage is higher than the first voltage for minimizing leakage current flowing in an unselected memory cell connected to the second line.

19. The resistive memory device of claim 16, wherein the voltage generator is further configured to generate a fourth voltage, a fifth voltage different from the fourth voltage, and a sixth voltage different from the fourth and fifth voltages, and

wherein the control logic is further configured to apply the fourth voltage to a first line, from among unselected second signal lines connected to the unselected memory cells, that is not adjacent to the selected second signal line;

to apply the fifth voltage to a second line, from among the unselected second signal lines, that is adjacent to the selected second signal line; and

to apply the sixth voltage to the selected second signal line as the first and second lines are floated.

20. The resistive memory device of claim 19, wherein the fourth voltage is equal to or higher than the first voltage, and the fifth voltage is higher than the fourth voltage, and the sixth voltage is lower than the fourth voltage.