Semiconductor device and method of forming the same

• US 9,184,091 B2
• Filed: 12/10/2013
• Issued: 11/10/2015
• Est. Priority Date: 02/19/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Song, Bo-Young, Yun, Cheol-Ju, Ko, Seung-Hee, Kim, Hyun-Gi, Lim, Chae-Ho, Kim, Jina
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US14/101,631
• Publication Number:
  US 20140231892A1
• Time in Patent Office: 700 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Claims

1. A semiconductor device comprising:

gate structures on a substrate;

first dopant regions and second dopant regions disposed at both sides of the gate structures;

conductive lines crossing the gate structures and connected to the first dopant regions, each of the conductive lines including a conductive pattern and a capping pattern on the conductive pattern;

contact structures provided between the conductive lines and connected to the second dopant regions;

spacer structures between the conductive lines and the contact structures,

wherein each of the contact structures includes a lower contact pattern on a respective second dopant region and an upper contact pattern on the lower contact pattern;

wherein a bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern; and

wherein each of the spacer structures includes an air gap, and an insulating spacer between the air gap and an adjacent contact structure; and

a capping spacer covering the air gap and the insulating spacer,

wherein a bottom surface of the capping spacer is in contact with a top surface of the lower contact pattern and the bottom surface of the upper contact pattern is lower than an interface between the capping spacer and the lower contact pattern.

2. The semiconductor device of claim 1 , wherein the bottom surface of the upper contact pattern is lower than a top surface of the air gap and a top surface of the insulating spacer.

3. The semiconductor device of claim 1, wherein the lower contact pattern includes a semiconductor;

and

wherein the upper contact pattern includes a metal.

4. The semiconductor device of claim 1, wherein a lower portion of the upper contact pattern is disposed within an upper portion of the lower contact pattern.

5. The semiconductor device of claim 1, further comprising:

fence patterns provided on the gate structures and extending along the gate structures,

wherein the contact structures are provided in contact holes defined by the conductive lines and the fence patterns.

6. The semiconductor device of claim 1, further comprising:

capacitors on the contact structures.

7. A semiconductor device comprising:

a substrate;

a plurality of bit line structures formed on the substrate, each bit line structure extending in a first direction,

wherein each bit line structure includes a first semiconductor layer, a conductive layer on the first semiconductor layer, and a capping layer on the conductive layer,

wherein the conductive layer is disposed above the first semiconductor layer and below the capping layer;

a plurality of word lines, each word line extending in a second direction different from the first direction;

a plurality of contact structures, each provided between two adjacent bit line structures of the plurality of bit line structures,

wherein each contact structure includes a lower contact portion and an upper contact portion, wherein a bottom surface of the upper contact portion contacts a top surface of the lower contact portion at a contact structure interface; and

a plurality of spacer structures, each spacer structure located between a bit line structure and a contact structure and including at least an air gap, an insulating spacer between the air gap and the contact structure, and a capping spacer, wherein

each capping spacer covers a top of a corresponding air gap, extends between a bit line structure and a contact structure from above the top of the corresponding air gap to a first height below the top of the corresponding air gap, and fills an area between the insulating spacer and the contact structure, wherein the first height is lower than a top of the conductive layer of a bit line structure adjacent to the capping spacer.

8. The semiconductor device of claim 7, wherein:

the contact structure interface for each contact structure is located at a second height lower than the first height.

9. The semiconductor device of claim 7, further comprising:

a first dopant region disposed below a first bit line structure of the plurality of bit line structures; and

a second dopant region disposed below a first contact structure of the plurality of contact structures.

10. The semiconductor device of claim 9, wherein:

the first dopant region contacts a first semiconductor layer of the first bit line structure; and

the second dopant region contacts the first contact structure.

11. The semiconductor device of claim 7, wherein:

for each capping spacer, the capping spacer fills an area between a corresponding insulating spacer and a corresponding bit line structure to a height above the first height and below a top of the corresponding insulating spacer.

12. A semiconductor device comprising:

gate structures on a substrate;

first dopant regions and second dopant regions disposed at both sides of the gate structures;

conductive lines crossing the gate structures and connected to the first dopant regions, each of the conductive lines including a conductive pattern and a capping pattern on the conductive pattern;

contact structures provided between the conductive lines and connected to the second dopant regions;

capacitors disposed on the contact structures and electrically connected to the second dopant regions through the contact structures,

wherein each of the contact structures includes a lower contact pattern on a respective second dopant region and an upper contact pattern including a material different from the lower contact pattern on the lower contact pattern; and

wherein a bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

13. The semiconductor device of claim 12, wherein a lower portion of the upper contact pattern is inserted in an upper portion of the lower contact pattern.

14. The semiconductor device of claim 12, further comprising:

spacer structures between the conductive lines and the contact structures,

wherein each of the spacer structures includes an air gap, and an insulating spacer between the air gap and an adjacent contact structure.

15. The semiconductor device of claim 14, wherein the bottom surface of the upper contact pattern is lower than a top surface of the air gap and a top surface of the insulating spacer.

16. The semiconductor device of claim 14, further comprising:

a capping spacer covering the air gap and the insulating spacer,

wherein a bottom surface of the capping spacer is in contact with a top surface of the lower contact pattern.

17. The semiconductor device of claim 12, wherein the lower contact pattern includes a semiconductor;

and

wherein the upper contact pattern includes a metal.