Semiconductor device and method of forming the same
First Claim
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1. A semiconductor device comprising:
- gate structures on a substrate;
first dopant regions and second dopant regions disposed at both sides of the gate structures;
conductive lines crossing the gate structures and connected to the first dopant regions, each of the conductive lines including a conductive pattern and a capping pattern on the conductive pattern;
contact structures provided between the conductive lines and connected to the second dopant regions;
spacer structures between the conductive lines and the contact structures,wherein each of the contact structures includes a lower contact pattern on a respective second dopant region and an upper contact pattern on the lower contact pattern;
wherein a bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern; and
wherein each of the spacer structures includes an air gap, and an insulating spacer between the air gap and an adjacent contact structure; and
a capping spacer covering the air gap and the insulating spacer,wherein a bottom surface of the capping spacer is in contact with a top surface of the lower contact pattern and the bottom surface of the upper contact pattern is lower than an interface between the capping spacer and the lower contact pattern.
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Abstract
First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.
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Citations
17 Claims
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1. A semiconductor device comprising:
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gate structures on a substrate; first dopant regions and second dopant regions disposed at both sides of the gate structures; conductive lines crossing the gate structures and connected to the first dopant regions, each of the conductive lines including a conductive pattern and a capping pattern on the conductive pattern; contact structures provided between the conductive lines and connected to the second dopant regions; spacer structures between the conductive lines and the contact structures, wherein each of the contact structures includes a lower contact pattern on a respective second dopant region and an upper contact pattern on the lower contact pattern; wherein a bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern; and wherein each of the spacer structures includes an air gap, and an insulating spacer between the air gap and an adjacent contact structure; and a capping spacer covering the air gap and the insulating spacer, wherein a bottom surface of the capping spacer is in contact with a top surface of the lower contact pattern and the bottom surface of the upper contact pattern is lower than an interface between the capping spacer and the lower contact pattern. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a substrate; a plurality of bit line structures formed on the substrate, each bit line structure extending in a first direction, wherein each bit line structure includes a first semiconductor layer, a conductive layer on the first semiconductor layer, and a capping layer on the conductive layer, wherein the conductive layer is disposed above the first semiconductor layer and below the capping layer; a plurality of word lines, each word line extending in a second direction different from the first direction; a plurality of contact structures, each provided between two adjacent bit line structures of the plurality of bit line structures, wherein each contact structure includes a lower contact portion and an upper contact portion, wherein a bottom surface of the upper contact portion contacts a top surface of the lower contact portion at a contact structure interface; and a plurality of spacer structures, each spacer structure located between a bit line structure and a contact structure and including at least an air gap, an insulating spacer between the air gap and the contact structure, and a capping spacer, wherein each capping spacer covers a top of a corresponding air gap, extends between a bit line structure and a contact structure from above the top of the corresponding air gap to a first height below the top of the corresponding air gap, and fills an area between the insulating spacer and the contact structure, wherein the first height is lower than a top of the conductive layer of a bit line structure adjacent to the capping spacer. - View Dependent Claims (8, 9, 10, 11)
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12. A semiconductor device comprising:
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gate structures on a substrate; first dopant regions and second dopant regions disposed at both sides of the gate structures; conductive lines crossing the gate structures and connected to the first dopant regions, each of the conductive lines including a conductive pattern and a capping pattern on the conductive pattern; contact structures provided between the conductive lines and connected to the second dopant regions; capacitors disposed on the contact structures and electrically connected to the second dopant regions through the contact structures, wherein each of the contact structures includes a lower contact pattern on a respective second dopant region and an upper contact pattern including a material different from the lower contact pattern on the lower contact pattern; and wherein a bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification