Semiconductor package and method therefor

• US 9,184,148 B2
• Filed: 10/22/2014
• Issued: 11/10/2015
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Jeon, Hyung Il, Chung, Ji Young, Kim, Byong Jin, Park, In Bae, Bae, Jae Min, Park, No Sun
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US14/521,417
• Publication Number:
  US 20150115422A1
• Time in Patent Office: 384 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16013 the bump connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/16258 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Claims

1. A semiconductor package comprising:

a plurality of leads, each lead having a bond finger;

a semiconductor chip having a plurality of conductive bumps, each conductive bump including a conductive pillar and a solder portion, each conductive bump attached to one of the bond fingers; and

a molding compound resin molded to seal the semiconductor chip, at least portions of the leads, and the conductive bump, wherein a width of the conductive pillar is larger than a width of each of the leads, and wherein the solder portion extends beyond an upper surface of the bond finger and at least partially surrounds a surface area of a portion of the bond finger.

2. The semiconductor package of claim 1, wherein the solder portion completely surrounds the surface area of the portion of the bond finger.

3. The semiconductor package of claim 1, wherein at least a portion of the surface area comprises a concave portion.

4. The semiconductor package of claim 1, wherein each bond finger has concave portions on opposing side surfaces in cross-sectional view.

5. The semiconductor package of claim 4 further comprising a dimple in a major surface of the bond finger, wherein the dimple is disposed between the concave portions.

6. The semiconductor package of claim 1, wherein a portion of the bond finger where the conductive bump is attached comprises a narrow neck, which has a width smaller than another width of the bond finger.

7. The semiconductor package of claim 1 further comprising a dimple in a major surface of the bond finger, at least a portion of the solder portion disposed within the dimple.

8. The semiconductor package of claim 7, wherein the dimple is in an upper major surface of the bond finger adjacent the semiconductor chip.

9. The semiconductor package of claim 1, wherein the semiconductor package has a bump-to-lead width ratio of about 2 or more.

10. The semiconductor package of claim 9, wherein the semiconductor package comprises a micro lead frame package.

11. An electronic package structure comprising:

a lead having a first width;

an electronic chip having a conductive bump on a major surface, wherein the conductive bump has a second width greater than the first width, and wherein the conductive bump is attached to the lead, wherein a portion of the conductive bump extends to at least partially surround a side surface of the lead; and

a molding compound resin sealing the electronic chip, the conductive bump, and at least a portion of the lead.

12. The structure of claim 11, wherein the lead further comprises a bond finger having the first width, wherein the conductive bump is attached to the bond finger.

13. The structure of claim 11, wherein side surfaces of the lead have concave portions.

14. The structure of claim 11 further comprising a dimple in a major surface of the lead, wherein a portion of the conductive bump is within the dimple.

15. The structure of claim 11, wherein the portion of the conductive bump completely surrounds a portion of the lead.

16. The structure of claim 11, wherein the conductive bump comprises a conductive pillar and a solder portion on a tip of the conductive pillar, wherein the solder portion extends to at least partially cover sides surfaces of the lead.

17. The structure of claim 11, wherein the lead further comprises a narrow neck portion, the narrow neck portion having the first width, and wherein the lead has a third width greater than the first width.

18. The structure of claim 11, wherein the second width to first width ratio is 2 or more.

19. A method for forming a semiconductor package comprising:

providing a lead frame having a lead, the lead having a first width;

providing a semiconductor chip having a conductive bump on a major surface, the conductive bump having a second width greater than the first width;

attaching the conductive bump to the lead, wherein after attaching the attaching step, a portion of the conductive bump extends to at least partially surround side surfaces of the lead; and

encapsulating the semiconductor chip, the conductive bump, and at least portions of the lead.

20. The method of claim 19, wherein:

providing the lead frame includes providing a lead having one or more of;

a concave portion on a side surface of lead, a narrow neck portion, or a dimple in an upper surface of the lead;

providing the conductive bump comprises providing a conductive pillar having a solder portion on an end surface of the conductive pillar; and

the second width to first width ratio is greater than or equal to about 2.