Simplified pitch doubling process flow

• US 9,184,159 B2
• Filed: 12/21/2012
• Issued: 11/10/2015
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Niroomand, Ardavan, Zhou, Baosuo, Alapati, Ramakanth
• Primary Examiner(s): Lee, Jae
• Application Number:
  US13/725,915
• Publication Number:
  US 20130105937A1
• Time in Patent Office: 1,054 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Claims

1. A partially formed integrated circuit, comprising:

a substrate;

a plurality of mandrels overlying the substrate, each mandrel having a long dimension and a short dimension as seen in a top-down view;

a plurality of spacer loops disposed at sidewalls of the mandrels;

a hard mask layer disposed on a same level as the spacer loops; and

a mask disposed directly over the hard mask layer and ends of the spacer loops disposed at sidewalls of the mandrels, while leaving mid-sections of the spacer loops exposed, wherein the mid-sections are disposed between opposing ends of each spacer loop, and wherein each mid-section comprises a spacer portion immediately adjacent a midpoint of the long dimension of the mandrels.

2. The partially formed integrated circuit of claim 1, wherein the mandrels comprise a carbon-containing material.

3. The partially formed integrated circuit of claim 2, wherein the mandrels comprise photoresist.

4. The partially formed integrated circuit of claim 2, wherein the spacer loop and the hard mask layer are formed of a same material.

5. The partially formed integrated circuit of claim 4, wherein the spacer loop and the hard mask layer are formed of an oxide.

6. The method of claim 1, wherein the mandrels and the mask are formed of a same material.

7. The method of claim 1, wherein the mandrels and the mask are formed of photoresist.

8. The partially formed integrated circuit of claim 1, wherein the spacers and the hard mask layer extend over and directly contact an underlying other hard mask layer disposed between the hard mask layer and the substrate.

9. The partially formed integrated circuit of claim 1, wherein the mask is a photoresist mask.

10. The partially formed integrated circuit of claim 1, wherein the mask comprises a spin-on antireflective coating.

11. The partially formed integrated circuit of claim 1, wherein the substrate comprises a plurality of layers of different materials.

12. The partially formed integrated circuit of claim 11, wherein the plurality of layers corresponds to layers in a control gate stack.

13. The partially formed integrated circuit of claim 1, wherein the partially formed integrated circuit is selected from the group consisting of a partially formed memory device and a partially formed computer processor.

14. A partially formed integrated circuit, comprising:

a plurality of spacer loops formed of spacer material and disposed directly adjacent a plurality of mandrels, the spacer loops and mandrels overlying and in contact with an underlying layer, wherein each mandrel has a long dimension and a short dimension as seen in a top-down view;

a layer of spacer material on the underlying layer; and

a patterned protective layer directly overlying ends of the spacer loops disposed directly adjacent the plurality of mandrels, wherein the protective layer leaves exposed mid-sections of the spacer loops between opposing ends of each spacer loop and wherein each mid-section comprises a spacer portion immediately adjacent a midpoint of the long dimension of the mandrels.

15. The partially formed integrated circuit of claim 14, wherein the underlying layer comprises a hard mask layer, the hard mask layer disposed over a substrate.

16. The partially formed integrated circuit of claim 15, wherein the hard mask layer comprises amorphous carbon.

17. The partially formed integrated circuit of claim 14, wherein the patterned protective layer comprises a pattern having features corresponding to one or more of landing pads, transistors, and local interconnects.

18. A partially formed integrated circuit, comprising:

a plurality of mandrels extending across an array region and into a peripheral region of the partially formed integrated circuit;

a plurality of spacer loops formed of spacer material extending along sidewalls of the mandrels, wherein ends of the spacer loops are disposed in the peripheral region;

a layer of spacer material disposed in the peripheral region and on a same level as the spacers; and

a mask disposed directly over the layer of spacer material and the ends of the spacer loops extending on sidewalls of the mandrels, while leaving exposed portions of the spacer loops in the array region.

19. The partially formed integrated circuit of claim 18, wherein the mandrels define parallel, regularly spaced-apart lines.

20. The partially formed integrated circuit of claim 19, wherein the mandrels have a pitch less than about 120 nm.