Semiconductor device and method for fabricating the same

• US 9,184,245 B2
• Filed: 08/06/2013
• Issued: 11/10/2015
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Lee, Jae
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US13/959,900
• Publication Number:
  US 20140042436A1
• Time in Patent Office: 826 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first to a third oxide semiconductor layers are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first and the third oxide semiconductor layers are each an amorphous semiconductor film. The second oxide semiconductor layer is a crystalline semiconductor film.

Claims

1. A semiconductor device comprising:

a first oxide insulating layer over a semiconductor substrate;

a first oxide semiconductor layer over the first oxide insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a second oxide insulating layer over the third oxide semiconductor layer; and

a first gate electrode layer overlapping with at least the second oxide semiconductor layer with the second oxide insulating layer provided therebetween,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each comprise indium,

wherein a proportion of indium in the second oxide semiconductor layer is higher than a proportion of indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a crystalline structure,

wherein the third oxide semiconductor layer and a side surface of the second oxide semiconductor layer are in contact with each other,

wherein the third oxide semiconductor layer and the first oxide semiconductor layer are in contact with each other, and

wherein the third oxide semiconductor layer and the first oxide insulating layer are in direct contact with each other.

2. The semiconductor device according to claim 1, further comprising:

a first nitride insulating layer between the semiconductor substrate and the first oxide insulating layer; and

a second nitride insulating layer between the second oxide insulating layer and the first gate electrode layer.

3. The semiconductor device according to claim 1, wherein, in an oxide semiconductor stack comprising the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer, an absorption coefficient due to a localized state is lower than or equal to 3×

10<sup>−

3</sup>/cm.

4. The semiconductor device according to claim 1, wherein a proportion of at least indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than or equal to 1×

10¹⁹ atoms/cm³.

5. The semiconductor device according to claim 1, further comprising a second gate electrode layer overlapping with at least the second oxide semiconductor layer with the first oxide insulating layer provided therebetween.

6. The semiconductor device according to claim 1, wherein the first oxide insulating layer and the second oxide insulating layer each contain oxygen in excess of a stoichiometric composition.

7. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has a crystal whose c-axis is aligned in a direction approximately perpendicular to a surface of the second oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each contain indium, zinc, and gallium.

9. The semiconductor device according to claim 1, wherein a concentration of silicon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm³.

10. The semiconductor device according to claim 1, wherein a concentration of carbon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm³.

11. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the third oxide semiconductor layer are amorphous.

12. The semiconductor device according to claim 1, further comprising;

a source electrode over and in contact with the third oxide semiconductor layer; and

a drain electrode over and in contact with the third oxide semiconductor layer,

wherein the third oxide semiconductor layer which does not overlap with the source electrode and the drain electrode has a smaller thickness than a region overlapping with the source electrode and the drain electrode.

13. A semiconductor device comprising:

a first oxide insulating layer comprising aluminum oxide over a semiconductor substrate;

a first oxide semiconductor layer over the first oxide insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer over the second oxide semiconductor layer;

a second oxide insulating layer over the third oxide semiconductor layer; and

a first gate electrode layer overlapping with at least the second oxide semiconductor layer with the second oxide insulating layer provided therebetween,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each comprise indium,

wherein a proportion of indium in the second oxide semiconductor layer is higher than a proportion of indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the third oxide semiconductor layer and a side surface of the second oxide semiconductor layer are in contact with each other,

wherein the third oxide semiconductor layer and the first oxide semiconductor layer are in contact with each other, and

wherein the third oxide semiconductor layer and the first oxide insulating layer are in direct contact with each other.

14. The semiconductor device according to claim 13, further comprising:

a first nitride insulating layer between the semiconductor substrate and the first oxide insulating layer; and

a second nitride insulating layer between the second oxide insulating layer and the first gate electrode layer.

15. The semiconductor device according to claim 13, wherein, in an oxide semiconductor stack comprising the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer, an absorption coefficient due to a localized state is lower than or equal to 3×

10<sup>−

3</sup>/cm.

16. The semiconductor device according to claim 13, wherein a proportion of at least indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than or equal to 1×

10¹⁹ atoms/cm³.

17. The semiconductor device according to claim 13, further comprising a second gate electrode layer overlapping with at least the second oxide semiconductor layer with the first oxide insulating layer provided therebetween.

18. The semiconductor device according to claim 13, wherein the first oxide insulating layer and the second oxide insulating layer each contain oxygen in excess of a stoichiometric composition.

19. The semiconductor device according to claim 13, wherein the second oxide semiconductor layer has a crystal whose c-axis is aligned in a direction approximately perpendicular to a surface of the second oxide semiconductor layer.

20. The semiconductor device according to claim 13, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each contain indium, zinc, and gallium.

21. The semiconductor device according to claim 13, wherein a concentration of silicon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm³.

22. The semiconductor device according to claim 13, wherein a concentration of carbon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm³.

23. The semiconductor device according to claim 13, wherein the first oxide semiconductor layer and the third oxide semiconductor layer are amorphous.

24. The semiconductor device according to claim 13, further comprising;

a source electrode over and in contact with the third oxide semiconductor layer; and

a drain electrode over and in contact with the third oxide semiconductor layer,

wherein the third oxide semiconductor layer which does not overlap with the source electrode and the drain electrode has a smaller thickness than a region overlapping with the source electrode and the drain electrode.