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Vertical power MOSFET having planar channel and its method of fabrication

  • US 9,184,248 B2
  • Filed: 02/06/2015
  • Issued: 11/10/2015
  • Est. Priority Date: 02/04/2014
  • Status: Active Grant
First Claim
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1. A vertical transistor comprisinga semiconductor substrate having a first electrode on its bottom surface;

  • a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration;

    a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;

    a trench having a vertical sidewall adjoining the second layer;

    a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;

    a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;

    a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage,the gate having a vertical extension facing the vertical sidewall and insulated from the sidewall;

    a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall; and

    a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate.

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