Vertical power MOSFET having planar channel and its method of fabrication
First Claim
1. A vertical transistor comprisinga semiconductor substrate having a first electrode on its bottom surface;
- a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration;
a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;
a trench having a vertical sidewall adjoining the second layer;
a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;
a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;
a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage,the gate having a vertical extension facing the vertical sidewall and insulated from the sidewall;
a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall; and
a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate.
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Accused Products
Abstract
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.
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Citations
21 Claims
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1. A vertical transistor comprising
a semiconductor substrate having a first electrode on its bottom surface; -
a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration; a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface; a trench having a vertical sidewall adjoining the second layer; a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface; a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate; a conductive gate overlying the channel for creating a lateral conductive path in the channel when the gate is biased above a threshold voltage, the gate having a vertical extension facing the vertical sidewall and insulated from the sidewall; a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall; and a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a current flows between the channel and the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification