Semiconductor arrangement and formation thereof

• US 9,184,250 B1
• Filed: 05/29/2014
• Issued: 11/10/2015
• Est. Priority Date: 05/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chih-Liang, Chang, Helen Shu-Hui, Young, Charles Chew-Yuen, Tzeng, Jiann-Tyng, Lin, Wei-Cheng, Sio, Kam-Tou
• Primary Examiner(s): Booth, Richard
• Application Number:
  US14/289,694
• Publication Number:
  US 20150349071A1
• Time in Patent Office: 530 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence

Abstract

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance.

Claims

1. A semiconductor arrangement comprising:

a first gate having a first gate height and a first gate length, the first gate adjacent a first contact having a first contact width, a first bottom contact length and a first top contact length lying within a first top contact length plane, the first top contact length plane a first critical contact distance from a bottom surface of the first contact; and

a second gate having a second gate height and a second gate length a first pitch distance from the first gate, the second gate adjacent the first contact, such that the first contact is between the first gate and the second gate, where dimensions of the semiconductor arrangement conform to

2. The semiconductor arrangement of claim 1, where the dimensions of the semiconductor arrangement conform to W≧

k7×

L, where

W is a sum of contact widths of contacts between the first gate and the second gate,

k7 is a seventh constant of about 1.48 to about 1.52, and

L is at least one of the first gate length or the second gate length.

3. The semiconductor arrangement of claim 1, where the dimensions of the semiconductor arrangement conform to C_tl≧

(k8×

H)+(k9×

L), where

C_tl is the first top contact length,

k8 is an eighth constant of about 0.18 to about 0.22,

H is at least one of the first gate height or the second gate height,

k9 is a ninth constant of about 0.74 to about 0.78, and

L is at least one of the first gate length or the second gate length.

4. The semiconductor arrangement of claim 1, where the dimensions of the semiconductor arrangement conform to C_bl≧

(k10×

H)+(k11×

L), where

C_bl is the first bottom contact length,

k10 is a tenth constant of about 0.14 to about 0.18,

H is at least one of the first gate height or the second gate height,

k11 is an eleventh constant of about 0.66 to about 0.70, and

L is at least one of first gate length or the second gate length.

5. The semiconductor arrangement of claim 1, where the dimensions of the semiconductor arrangement conform to C_al≧

(k12×

H)+(k13×

L), where

C_al is a first average length comprising an average of the first bottom contact length and the first top contact length,

k12 is a twelfth constant of about 0.18 to about 0.22,

H is at least one of the first gate height or the second gate height,

k13 is a thirteenth constant of about 0.68 to about 0.72, and

L is at least one of the first gate length or the second gate length.

6. The semiconductor arrangement of claim 1, comprising:

a second contact between the second gate and a third gate having a third gate height and a third gate length, the second contact having a second contact width, a second bottom contact length and a second top contact length lying within a second top contact length plane, the second top contact length plane a second critical contact distance from a bottom surface of the second contact; and

a third contact between the second gate and the third gate, the third contact having a third contact width, a third bottom contact length and a third top contact length lying within a third top contact length plane, the third top contact length plane a third critical contact distance from a bottom surface of the third contact.

7. The semiconductor arrangement of claim 6, where the dimensions of the semiconductor arrangement conform to D_c=k1×

L, where

D_c is at least one of the first critical contact distance, the second critical contact distance or the third critical contact distance,

k1 is a first constant of about 1.58 to about 1.62, and

L is at least one of the first gate length, the second gate length or the third gate length.

8. The semiconductor arrangement of claim 6, where the dimensions of the semiconductor arrangement conform to C_tl≧

(k8×

H)+(k9×

L), where

C_tl is a top contact length average of the second top contact length and the third top contact length,

k8 is an eighth constant of about 0.18 to about 0.22,

H is at least one of the second gate height or the third gate height,

k9 is a ninth constant of about 0.74 to about 0.78, and

L is at least one of the second gate length or the third gate length.

9. The semiconductor arrangement of claim 6, where the dimensions of the semiconductor arrangement conform to C_bl≧

(k10×

H)+(k11×

L), where

C_bl is a bottom contact length average of the second bottom contact length and the third bottom contact length,

k10 is a tenth constant of about 0.14 to about 0.18,

H is at least one of the second gate height or the third gate height,

K11 is an eleventh constant of about 0.66 to about 0.70, and

L is at least one of second gate length or the third gate length.

10. The semiconductor arrangement of claim 6, where the dimensions of the semiconductor arrangement conform to C_al≧

(k12×

H)+(k13×

L), where

C_al is a second average length comprising an average of the second bottom contact length, the third bottom contact length, the second top contact length and the third top contact length,

k12 is a twelfth constant of about 0.18 to about 0.22,

H is at least one of the second gate height or the third gate height,

k13 is a thirteenth constant of about 0.68 to about 0.72, and

L is at least one of the second gate length or the third gate length.

11. A semiconductor arrangement comprising:

a first gate having a first gate height and a first gate length, the first gate adjacent a first contact having a first contact width, a first bottom contact length and a first top contact length lying within a first top contact length plane; and

a second gate having a second gate height and a second gate length a first pitch distance from the first gate, the second gate adjacent the first contact, such that the first contact is between the first gate and the second gate, where dimensions of the semiconductor arrangement conform to

12. The semiconductor arrangement of claim 11, where the dimensions of the semiconductor arrangement conform to C_tl≧

(k8×

H)+(k9×

L), where

C_tl is the first top contact length,

k8 is an eighth constant of about 0.18 to about 0.22,

H is at least one of the first gate height or the second gate height,

k9 is a ninth constant of about 0.74 to about 0.78, and

L is at least one of the first gate length or the second gate length.

13. The semiconductor arrangement of claim 11, where the dimensions of the semiconductor arrangement conform to C_bl≧

(k10×

H)+(k11×

L), where

C_bl is the first bottom contact length,

k10 is a tenth constant of about 0.14 to about 0.18,

H is at least one of the first gate height or the second gate height,

K11 is an eleventh constant of about 0.66 to about 0.70, and

L is at least one of first gate length or the second gate length.

14. The semiconductor arrangement of claim 11, where the dimensions of the semiconductor arrangement conform to C_al≧

(k12×

H)+(k13×

L), where

C_al is a first average length comprising an average of the first bottom contact length and the first top contact length,

k12 is a twelfth constant of about 0.18 to about 0.22,

H is at least one of the first gate height or the second gate height,

k13 is a thirteenth constant of about 0.68 to about 0.72, and

L is at least one of the first gate length or the second gate length.

15. The semiconductor arrangement of claim 11, the first top contact length plane a first critical contact distance from a bottom surface of the first contact, where the dimensions of the semiconductor arrangement conform to D_c=k1×

L, where

D_c is the first critical contact distance,

k1 is a first constant of about 1.58 to about 1.62, and

L is at least one of the first gate length or the second gate length.

16. A semiconductor arrangement comprising:

a gate having a gate length and a gate height; and

a contact adjacent the gate, where a bottom surface of the contact has a bottom contact length that is greater than or equal to (k10×

H)+(k11×

L), where

k10 is a tenth constant of about 0.14 to about 0.18,

H is the gate height,

K11 is an eleventh constant of about 0.66 to about 0.70, and

L is the gate length.

17. The semiconductor arrangement of claim 16, the contact comprising a critical contact region extending from the bottom surface to a top contact length plane, the top contact length plane a critical contact distance from the bottom surface, the critical contact distance conforming to (k1×

L), where

k1 is a first constant of about 1.58 to about 1.62, and

L is the gate length.

18. The semiconductor arrangement of claim 17, wherein the contact has a top contact length at the top contact length plane, the top contact length greater than or equal to (k8×

H)+(k9×

L), where

k8 is an eighth constant of about 0.18 to about 0.22,

H is the gate height, and

k9 is a ninth constant of about 0.74 to about 0.78, and

L is the gate length.

19. The semiconductor arrangement of claim 17, wherein an average length of the critical contact region is greater than or equal to (k12×

H)+(k13×

L), where

k12 is a twelfth constant of about 0.18 to about 0.22,

H is the gate height,

k13 is a thirteenth constant of about 0.68 to about 0.72, and

L is the gate length.

20. The semiconductor arrangement of claim 16, comprising a fin, wherein the gate surrounds at least 3 sides of the fin.