Semiconductor device having dual parallel channel structure and method of fabricating the same

• US 9,184,280 B2
• Filed: 08/06/2013
• Issued: 11/10/2015
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Um, Chang-yong, Shin, Jai-kwang
• Primary Examiner(s): MOORE, WHITNEY
• Application Number:
  US13/960,333
• Publication Number:
  US 20140197479A1
• Time in Patent Office: 826 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).

Claims

1. A semiconductor device, comprising:

a gate arranged along side walls of a trench;

a gate oxide layer between the side walls of the trench and the gate and between a bottom surface of the trench and the gate;

a first source region disposed to face an upper portion of the gate, the first source region being doped to a first conduction type;

a second source region on the bottom surface of the trench, the second source region being of the first conduction type;

a first well region on a lower surface of the first source region; and

a second well region on a lower surface of the second source region, the first and second well regions doped to a second conduction type, the second conduction type being electrically opposite to the first conduction type.

2. The semiconductor device as claimed in claim 1, wherein the gate is circular, polygonal ring-shaped, or linear-shaped.

3. The semiconductor device as claimed in claim 1, wherein the gate oxide layer exposes a central portion of the bottom surface of the trench.

4. The semiconductor device as claimed in claim 1, wherein

the second source region is partially present on the bottom surface of the trench, the second source region surrounding a central portion of the bottom surface of the trench,

the gate overlaps an edge of the second source region, and

the first source region faces an upper portion of a side surface of the gate.

5. The semiconductor device as claimed in claim 1, wherein the first and second source regions are N+-doped, and the first and second well regions are P-doped.

6. The semiconductor device as claimed in claim 1, wherein

the first well region is below an entirety of the first source region,

the second well region entirely surrounds a bottom surface and side walls of the second source region, and

the gate overlaps a part of the second well region that surrounds the side walls of the second source region.

7. The semiconductor device of claim 1, further comprising:

a substrate including a drift region, the drift region being doped to the first conduction type.

8. The semiconductor device of claim 7, wherein the first source region is on an upper surface of the substrate.

9. The semiconductor device of claim 7, wherein the first well region is between the first source region and the drift region.

10. The semiconductor device of claim 7, wherein the second well region is between the second source region and the drift region.

11. The semiconductor device as claimed in claim 7, further comprising:

a drain electrode on a lower surface of the substrate;

a source electrode on the substrate and in the trench so as to be electrically connected to the first and second source regions; and

an interlayer insulating layer covering the gate and the gate oxide layer such that the gate and the gate oxide layer do not contact the source electrode.

12. The semiconductor device as claimed in claim 11, further comprising:

a first ohmic contact layer between the first well region and the source electrode so as to provide ohmic contact between the source electrode and the first source region; and

a second ohmic contact layer in a central portion of the second source region so as to provide ohmic contact between the source electrode and the second source region,

wherein the first and second ohmic contact layers are doped to the second conduction type.

13. The semiconductor device as claimed in claim 12, wherein

the first ohmic contact layer is on the first well region so as to be adjacent to the first source region, and

the second ohmic contact layer is on the second well region so as to be adjacent to the second source region.

14. The semiconductor device as claimed in claim 7, wherein

the substrate includes a lower region, the drift region being on the lower region,

the lower region and the drift region are doped to the first conduction type, a doping concentration of the drift region being lower than that of the lower region, and

the lower region of the substrate is N+-doped and the drift region is N-doped.