Multi-source JFET device

• US 9,184,304 B2
• Filed: 01/23/2014
• Issued: 11/10/2015
• Est. Priority Date: 04/12/2013
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Young Bae, Oh, In Taek, Kim, Kwang Il, Lee, Kyung Ho
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US14/162,561
• Publication Number:
  US 20140306270A1
• Time in Patent Office: 656 Days
• Field of Search: 257/133, 257/169, 257/173, 257/256, 257/272, 257/134, 438/186
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A junction field-effect transistor (JFET) device is provided. The JFET includes a drain region, a source region, and a junction gate region disposed between the drain region and the source region, and the source region includes two or more source terminals.

Claims

1. A junction field-effect transistor (JFET) device, comprising:

a drain region;

a junction gate region surrounding the drain region; and

a plurality of source regions surrounding the junction gate region.

2. The JFET device of claim 1, further comprising a well region disposed below the drain region, the junction gate region and the plurality of source regions,

wherein the well region below the junction gate region has a greater depth than the well region below the drain region and the plurality of source regions.

3. The JFET device of claim 2, wherein silicide is disposed on the drain region, the junction gate region and the plurality of source regions.

4. The JFET device of claim 2, further comprising:

an insulating layer disposed on a surface of a substrate;

a barrier layer disposed below the insulating layer; and

a plate disposed on the insulating layer to alleviate electric field at a lower region of the barrier layer.

5. The JFET device of claim 4, wherein the plate comprises polycrystal silicon (Poly-Si) or metal.

6. The JFET device of claim 1, further comprising a source region isolating portion that isolates the plurality of source regions from each other.

7. The JFET device of claim 6, wherein the source region isolating portion comprises a region doped with a dopant that is different type from the dopant forming the source terminals.

8. The JFET device of claim 6, wherein the source region isolating portion comprises a body region doped at a first concentration with dopant type different from that of the plurality of source regions, and a well region surrounding the body region and doped at a second concentration that is lower than the first concentration.

9. The JFET device of claim 6, wherein the JFET device is configured to control current amount based on connecting of the plurality of source regions.

10. The JFET device of claim 9, wherein the plurality of source regions are floated when not involved with electric current supply.

11. The JFET device of claim 6, wherein the plurality of source regions have same area or different areas from each other.

12. A junction field-effect transistor (JFET) device, comprising a drain region, a plurality of source regions, and a junction gate region disposed between the drain region and the plurality of source regions.

13. The JFET device of claim 12, wherein the plurality of source regions has a shape of a circular region disposed above a well region;

and the plurality of source regions have a shape of an arc.

14. The JFET device of claim 12, wherein the plurality of source regions are doped with a first conductivity type, and are separated from each other by source region isolating portions that are doped with a second conductivity type.