Semiconductor device which generates a DC power supply from an AC power supply

• US 9,184,671 B2
• Filed: 11/05/2014
• Issued: 11/10/2015
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yoshida, Yoichi
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US14/534,105
• Publication Number:
  US 20150280606A1
• Time in Patent Office: 370 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 7/02 Conversion of ac power input into dc power output without possibility of reversal
• CPC Class Codes: H02M 7/103 Containing passive elements (capacitively coupled) which are ordered in cascade on one source
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A semiconductor device according to one embodiment includes first and second transistor columns which each include a NMOS transistor and a PMOS transistor which are connected in series between a first power wire and a second power wire. Further, a gate of the PMOS transistor of one transistor column is connected to a wire which connects the NMOS transistor and the PMOS transistor of the other transistor column. Furthermore, an AC signal obtained by superimposing a signal on a bias voltage which is a voltage lower than that of the gate of the PMOS transistor included in the same transistor column is supplied to the gate of the NMOS transistor included in the transistor column.

Claims

1. A semiconductor device comprising a rectifier circuit, wherein the rectifier circuit includes:

first and second input wires to which AC signals whose phases are inverted from each other are transmitted;

a first transistor of a first conductive type that includes a first power wire connected with a first transistor terminal and a gate connected with the first input wire;

a second transistor of the first conductive type that includes the first power wire connected with the first transistor terminal, and a gate connected with the second input wire;

a first capacitor that includes one end connected to the first input wire;

a second capacitor that includes one end connected to the second input wire;

a third transistor of a second conductive type that includes a second power wire connected with a first transistor terminal and a gate connected with an other end of the first capacitor;

a fourth transistor of the second conductive type that includes the second power wire connected with a first transistor terminal and a gate connected to an other end of the second capacitor;

a first inter-element wire that connects a second transistor terminal of the second transistor, a second transistor terminal of the fourth transistor and the gate of the third transistor; and

a second inter-element wire that connects a second transistor terminal of the first transistor, a second transistor terminal of the third transistor and the gate of the fourth transistor.

2. The semiconductor device according to claim 1, further comprising a bias circuit that generates the AC signal by superimposing on a bias voltage a signal obtained from a signal source of the AC signal.

3. The semiconductor device according to claim 2, wherein the bias circuit is a resonance circuit.

4. The semiconductor device according to claim 1, further comprising a third capacitor that is connected between the first power wire and the second power wire.

5. The semiconductor device according to claim 1, further comprising:

a fifth transistor of the second conductive type that includes a second transistor terminal connected to the second inter-element wire and a gate connected to the other end of the first capacitor;

a sixth transistor of the second conductive type that includes a second transistor terminal connected to the first inter-element wire and a gate connected to the other end of the second capacitor; and

a seventh transistor of the first conductive type that is inserted in the second power wire and includes a gate connected to a first transistor terminal of the fifth transistor and a first transistor terminal of the sixth transistor.

6. The semiconductor device according to claim 1, further comprising:

a plurality of rectifier circuits that is formed by connecting in cascade a first output terminal provided on the first power wire and a second output terminal provided on the second power wire; and

a smoothing capacitor that is connected between the first power wire of the rectifier circuit arranged at a first stage and the second power wire of the rectifier circuit arranged at a final stage.

7. The semiconductor device according to claim 1, further comprising:

a plurality of rectifier circuits that includes loads connected with a first output terminal provided on the first power wire through a common wire, respectively; and

a smoothing capacitor that is connected between the common wire and a ground wire.

8. The semiconductor device according to claim 1, further comprising a power circuit that is connected between the first power wire and the second power wire, and that generates a second power voltage by performing at least one of stepping up and stepping down of a first power voltage transmitted through the second power wire.