System and method of analog-to-digital converters

• US 9,184,758 B2
• Filed: 02/07/2013
• Issued: 11/10/2015
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Ali, Ahmed Mohamed Abdelatty
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US13/761,288
• Publication Number:
  US 20130176152A1
• Time in Patent Office: 1,006 Days
• Field of Search: 341/120, 341/155.144, 341/161, 341/118
• US Class Current: 1/1
• CPC Class Codes: H03M 1/1014 at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence

Abstract

An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Claims

1. An analog-to-digital converter (ADC) system for converting an input, comprising:

a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration,

wherein;

for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,

the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage,

the amplified error is amplified in a second configuration of following signal converter stages, and

an error estimator is coupled to the pipeline to receive the amplified error and to adjust a gain of the amplifier based on the amplified error.

2. The ADC system of claim 1, wherein the amplified error is one of an analog error and a digital error.

3. The ADC system of claim 1, further comprising:

a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

4. The ADC system of claim 1, wherein the error estimator calculates the amplifier gain based on the amplified error up to the one of the signal converters.

5. The ADC system of claim 1, wherein the error estimator calculates a ratio factor between the summing node error and the input, and wherein the amplifier gain is adjusted based on the ratio factor.

6. The ADC system of claim 1, wherein the gain of the amplifier is adjusted to a maximum gain.

7. The ADC system of claim 1, wherein the gain of the amplifier is adjusted to a maximum gain regardless of changes in current supply and temperature.

8. The ADC system of claim 1, wherein the MDAC in the each signal converter switches between the first and second circuit configurations via a plurality of switches controlled according to a first clock.

9. The ADC system of claim 1, wherein the error estimator is selectively coupled to the pipeline according to a second clock which is independent of the first clock.

10. The ADC system of claim 1, wherein the first circuit configuration occurs during one of a first half clock cycle and a second half clock cycle of the first clock, and the second circuit configuration occurs during an opposite half clock cycle of the first circuit configuration.

11. The ADC system of claim 1, wherein signal converter stages in the pipeline operate alternatively in the first and second configurations.

12. A method for analog-to-digital conversion, comprising:

providing a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of an input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration,

wherein;

for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,

the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage,

the amplified error is amplified in a second configuration of following signal converter stages, and

providing an error estimator coupled to the pipeline to receive the amplified error and to adjust a gain of the amplifier based on the amplified error.

13. The method of claim 12, wherein the amplified error is one of an analog error and a digital error.

14. The method of claim 12, further comprising:

providing a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters.

15. The method of claim 12, wherein the error estimator calculates a ratio factor between the summing node error and the input, and wherein the amplifier gain is adjusted based on the ratio factor.

16. The method of claim 12, wherein the gain of the amplifier is adjusted to a maximum gain.

17. The method of claim 12, wherein the gain of the amplifier is adjusted to a maximum gain regardless of changes in current supply and temperature.

18. The method of claim 12, wherein the MDAC in the each signal converter switches between the first and second circuit configurations via a plurality of switches controlled according to a first clock.

19. The method of claim 12, wherein the error estimator is selectively coupled to the pipeline according to a second clock which is independent of the first clock.

20. An analog-to-digital converter (ADC) system for converting an input, comprising:

means for successively cascading signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration, wherein

for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,

the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage, and

the amplified error is amplified in a second configuration of following signal converter stages; and

means for receiving the amplified error and to adjust a gain of the amplifier based on the amplified error.