Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition

• US 9,184,850 B2
• Filed: 09/24/2014
• Issued: 11/10/2015
• Est. Priority Date: 02/05/2001
• Status: Expired due to Fees

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Aronson, Lewis B., Hosking, Lucy G.
• Primary Examiner(s): Sedighian, M. R.
• Application Number:
  US14/494,823
• Publication Number:
  US 20150139661A1
• Time in Patent Office: 412 Days
• Field of Search: 398/135, 398/138
• US Class Current: 1/1
• CPC Class Codes: G01M 11/00 Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
• CPC Class Codes: G01M 11/30 Testing of optical devices, constituted by fibre optics or optical waveguides
• CPC Class Codes: G01M 99/002 Thermal testing flaw detection G01N25/72
• CPC Class Codes: H04B 10/07 Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
• CPC Class Codes: H04B 10/0799 Monitoring line transmitter or line receiver equipment
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04B 2210/08 Shut-down or eye-safety

Abstract

An optoelectronic transceiver includes an optoelectronic transmitter, an optoelectronic receiver, memory, and an interface. The memory is configured to store digital values representative of operating conditions of the optoelectronic transceiver. The interface is configured to receive from a host a request for data associated with a particular memory address, and respond to the host with a specific digital value of the digital values. The specific digital value is associated with the particular memory address received from the host. The optoelectronic transceiver may further include comparison logic configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored as digital values in the memory.

Claims

1. A circuit for monitoring operation of an optoelectronic transceiver, which includes a laser transmitter and a photodiode receiver, said circuit comprising:

analog to digital conversion circuitry configured to convert at least two analog signals corresponding to operating conditions of said optoelectronic transceiver into a first digital value corresponding to a first operating condition and a second digital value corresponding to a second operating condition;

memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address, wherein the first address and second address are known to a host external to the optoelectronic transceiver; and

an interface configured to enable the host to access the first digital value using the first address and to access the second digital value using the second address.

2. The circuit of claim 1, wherein the first digital value is selected from a group consisting of:

a supply voltage measurement, a laser temperature measurement, a laser wavelength measurement, and a thermoelectric cooler current measurement.

3. The circuit of claim 1, wherein the first digital value includes a supply voltage measurement.

4. The circuit of claim 1, wherein the first digital value includes a laser temperature measurement.

5. The circuit of claim 1, wherein the first digital value includes a laser wavelength measurement.

6. The circuit of claim 1, wherein the first digital value includes a thermoelectric cooler current measurement.

7. The circuit of claim 1, further comprising a processor configured to store the first digital value in the first memory location and to store the second digital value in the second memory location.

8. The circuit of claim 7, wherein the processor is further configured to access the first digital value in the first memory location and to access the second digital value in the second memory location.

9. The circuit of claim 8, wherein the processor is further configured to access the first digital value in response to receiving the first address from the host and to access the second digital value in response to receiving the second address from the host.

10. The circuit of claim 9, wherein the processor is further configured to provide the digital values accessed by the processor to the host via the interface.

11. The circuit of claim 1, wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first digital value and the second digital value.

12. The circuit of claim 1, wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

13. The circuit of claim 1, wherein the circuit further comprises rate selection circuitry configured to set the photodiode receiver to a bandwidth in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

14. A circuit for monitoring operation of an optoelectronic transceiver, which includes a laser transmitter and a photodiode receiver, said circuit comprising:

analog to digital conversion circuitry configured to convert at least two analog signals corresponding to operating conditions of said optoelectronic transceiver into a first digital values corresponding to a first operating condition and a second digital value corresponding to a second operating condition;

memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address, wherein the first address and second address are known to a host external to the optoelectronic transceiver;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first flag value is stored in a first flag memory location that is mapped to a predefined and unique first flag memory address and the second flag value is stored in a second flag memory location that is mapped to a predefined and unique second flag memory address, wherein the first flag memory address and the second flag memory address are known to the host; and

an interface configured to enable the host to access the first digital value using the first address, to access the second digital value using the second address, to access the first flag value using the first flag memory address, and to access the second flag value using the second flag memory address.

15. The circuit of claim 14, further comprising a processor configured to store the first digital value in the first memory location, to store the second digital value in the second memory location, to store the first flag value in the first flag memory address, and to store the second flag value in the second flag memory address.

16. The circuit of claim 15, wherein the processor is further configured to access the first digital value in the first memory location, to access the second digital value in the second memory location, to access the first flag value in the first flag memory address, and to access the second flag value in the second flag memory address.

17. The circuit of claim 16, wherein the processor is further configured to access the first digital value in response to receiving the first address from the host, to access the second digital value in response to receiving the second address from the host, to access the first flag value in response to receiving the first flag memory address, and to access the second flag value in response to receiving the second flag memory address.

18. The circuit of claim 17, wherein the processor is further configured to provide the digital and flag values accessed by the processor to the host via the interface.

19. The circuit of claim 14, wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first flag value and the second flag value.

20. The circuit of claim 14, wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first flag value and the second flag value.

21. The circuit of claim 14, wherein the circuit further comprises rate selection circuitry configured to set the photodiode receiver to a bandwidth in response to a signal, wherein the signal is based on one or more of the first flag value and the second flag value.

22. The circuit of claim 14, wherein the first limit value corresponds to a high alarm limit value and the first flag value generated by the comparison of the first digital value and the first limit value is a high alarm flag.

23. The circuit of claim 14, wherein the first limit value corresponds to a low alarm limit value and the first flag value generated by the comparison of the first digital value and the first limit value is a low alarm flag.

24. The circuit of claim 14, wherein the first limit value corresponds to a high warning limit value and the first flag value generated by the comparison of the first digital value and the first limit value is a high warning flag.

25. The circuit of claim 14, wherein the first limit value corresponds to a low warning limit value and the first flag value generated by the comparison of the first digital value and the first limit value is a low warning flag.

26. The circuit of claim 14, wherein the first digital value includes a temperature measurement, the first limit value is a high temperature alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high temperature alarm.

27. The circuit of claim 14, wherein the first digital value includes a temperature measurement, the first limit value is a low temperature alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low temperature alarm.

28. The circuit of claim 14, wherein the first digital value includes a temperature measurement, the first limit value is a high temperature warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high temperature warning.

29. The circuit of claim 14, wherein the first digital value includes a temperature measurement, the first limit value is a low temperature warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low temperature warning.

30. The circuit of claim 14, wherein the first digital value includes a supply voltage measurement, the first limit value is a high supply voltage alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high supply voltage alarm.

31. The circuit of claim 14, wherein the first digital value includes a supply voltage measurement, the first limit value is a low supply voltage alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low supply voltage alarm.

32. The circuit of claim 14, wherein the first digital value includes a supply voltage measurement, the first limit value is a high supply voltage warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high supply voltage warning.

33. The circuit of claim 14, wherein the first digital value includes a supply voltage measurement, the first limit value is a low supply voltage warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low supply voltage warning.

34. The circuit of claim 14, wherein the first digital value includes a laser bias current measurement, the first limit value is a high laser bias current alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser bias current alarm.

35. The circuit of claim 14, wherein the first digital value includes a laser bias current measurement, the first limit value is a low laser bias current alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser bias current alarm.

36. The circuit of claim 14, wherein the first digital value includes a laser bias current measurement, the first limit value is a high laser bias current warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser bias current warning.

37. The circuit of claim 14, wherein the first digital value includes a laser bias current measurement, the first limit value is a low laser bias current warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser bias current warning.

38. The circuit of claim 14, wherein the first digital value includes a laser transmitter output power measurement, the first limit value is a high laser transmitter output power alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser transmitter output power alarm.

39. The circuit of claim 14, wherein the first digital value includes a laser transmitter output power measurement, the first limit value is a low laser transmitter output power alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser transmitter output power alarm.

40. The circuit of claim 14, wherein the first digital value includes a laser transmitter output power measurement, the first limit value is a high laser transmitter output power warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser transmitter output power warning.

41. The circuit of claim 14, wherein the first digital value includes a laser transmitter output power measurement, the first limit value is a low laser transmitter output power warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser transmitter output power warning.

42. The circuit of claim 14, wherein the first digital value includes a received power measurement, the first limit value is a high received power alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high received power alarm.

43. The circuit of claim 14, wherein the first digital value includes a received power measurement, the first limit value is a low received power alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low received power alarm.

44. The circuit of claim 14, wherein the first digital value includes a received power measurement, the first limit value is a high received power warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high received power warning.

45. The circuit of claim 14, wherein the first digital value includes a received power measurement, the first limit value is a low received power warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low received power warning.

46. The circuit of claim 14, wherein the first digital value includes a laser temperature measurement, the first limit value is a high laser temperature alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser temperature alarm.

47. The circuit of claim 14, wherein the first digital value includes a laser temperature measurement, the first limit value is a low laser temperature alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser temperature alarm.

48. The circuit of claim 14, wherein the first digital value includes a laser temperature measurement, the first limit value is a high laser temperature warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser temperature warning.

49. The circuit of claim 14, wherein the first digital value includes a laser temperature measurement, the first limit value is a low laser temperature warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser temperature warning.

50. The circuit of claim 14, wherein the first digital value includes a laser wavelength measurement, the first limit value is a high laser wavelength alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser wavelength alarm.

51. The circuit of claim 14, wherein the first digital value includes a laser wavelength measurement, the first limit value is a low laser wavelength alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser wavelength alarm.

52. The circuit of claim 14, wherein the first digital value includes a laser wavelength measurement, the first limit value is a high laser wavelength warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high laser wavelength warning.

53. The circuit of claim 14, wherein the first digital value includes a laser wavelength measurement, the first limit value is a low laser wavelength warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low laser wavelength warning.

54. The circuit of claim 14, wherein the first digital value includes a thermoelectric cooler current measurement, the first limit value is a high thermoelectric cooler current alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high thermoelectric cooler current alarm.

55. The circuit of claim 14, wherein the first digital value includes a thermoelectric cooler current measurement, the first limit value is a low thermoelectric cooler current alarm limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low thermoelectric cooler current alarm.

56. The circuit of claim 14, wherein the first digital value includes a thermoelectric cooler current measurement, the first limit value is a high thermoelectric cooler current warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a high thermoelectric cooler current warning.

57. The circuit of claim 14, wherein the first digital value includes a thermoelectric cooler current measurement, the first limit value is a low thermoelectric cooler current warning limit value, and the first flag value generated by the comparison of the first digital value and the first limit value is a low thermoelectric cooler current warning.