Performance based power management of a memory and a data storage system using the memory

• US 9,189,053 B2
• Filed: 09/23/2014
• Issued: 11/17/2015
• Est. Priority Date: 12/06/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cui, Jing, Zhang, Shayan, Zhao, Yunwu
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US14/493,353
• Publication Number:
  US 20150160718A1
• Time in Patent Office: 420 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. Voltage sensing circuitry senses a voltage level of the memory array and outputs a power status signal. The power status signal is used to determine when the memory array is awake and can be accessed.

Claims

1. An integrated circuit, comprising:

a memory circuit including a memory array;

a memory control unit that issues access requests to the memory circuit;

a power control circuit, coupled to the memory circuit, for controlling power supplied to the memory array and for controlling access to the memory array, wherein the power control circuit supplies the memory array with a supply voltage corresponding to one of a plurality of memory performance levels including a full performance level and at least one power-saving performance level; and

a power status feedback unit including a voltage sensing circuit coupled to the memory array for sensing a voltage level of the memory array, wherein the voltage sensing circuit generates a power status signal indicating one of the plurality of memory performance levels of the memory array depending upon the sensed voltage level, and wherein the power control circuit permits the access to the memory array depending upon the power status signal,

wherein the power status feedback unit further comprises a switch controller that processes the power status signal to generate a final power status signal for output to at least one of the power control circuit and the memory control unit; and

wherein the voltage sensing circuit and the switch controller are located in an always-on voltage domain such that they are operable in any one of the plurality of power-saving performance levels.

2. The integrated circuit of claim 1, wherein the voltage sensing circuit detects a transient dip in voltage having longer than a threshold voltage-dip duration when the memory array is in any one of the plurality of memory performance levels for which the corresponding supply voltage is sufficient to support data retention, and wherein the memory control unit triggers a lost-data recovery process in response to detection of the transient voltage dip.

3. The integrated circuit of claim 2, wherein the power status feedback unit further comprises a counter coupled to the voltage sensing circuit, wherein the counter maintains a count to determine if a voltage dip detected by the voltage sensing circuit has reached the threshold voltage-dip duration.

4. The integrated circuit of claim 1, wherein the at least one power-saving performance level comprises at least one of:

(i) a data-retaining power-saving performance level in which the supply voltage is sufficient to retain data stored in the memory array; and

(ii) a data-loss power-saving performance level in which the supply voltage is insufficient to retain data stored in the memory array.

5. The integrated circuit of claim 1, wherein different ones of the plurality of memory performance levels have at least one of different supply voltages and different characteristic clock frequencies.

6. The integrated circuit of claim 1, wherein the voltage sensing circuit outputs the power status signal indicating one of the plurality of memory performance levels depending upon a respective threshold proportion of a full supply voltage being attained by a currently sensed voltage level.

7. The integrated circuit of claim 6, wherein the voltage sensing circuit is configured to at least one of:

(i) output the power status signal corresponding to a full memory performance level when the currently sensed voltage level is greater than or equal to 95% of the full supply voltage;

(ii) to output the power status signal corresponding to a power-off memory performance level when the currently sensed voltage level is less than or equal to 5% of the full supply voltage;

(iii) to output the power status signal corresponding to a first reduced memory performance level when the currently sensed voltage level is less than 95% of the full supply voltage and greater than or equal to 80% of the full supply voltage; and

(iv) to output the power status signal corresponding to a second reduced memory performance level when the currently sensed voltage level is less than 80% of the full supply voltage and greater than or equal to 70% of the full supply voltage.

8. The integrated circuit of claim 1, wherein the memory array comprises a plurality of SRAM memory arrays and wherein a set of voltage sensing circuits is provided for each of a respective plurality of memory array subsets, each subset comprising at least one of the plurality of SRAM memory arrays.

9. The integrated circuit of claim 8, wherein the voltage sensing circuits are integrated within corresponding ones of the memory arrays.

10. The integrated circuit of claim 1, wherein the power status feedback unit further comprises a counter connected to the voltage sensing circuit, wherein the counter maintains a count for performing sleep time control for the memory array, wherein the sleep time is a time when the memory performance level of the memory array is a sleep state corresponding to one of the at least one power-saving performance levels and wherein the counter is triggered to start counting by the power status signal and performs a count based on a predetermined minimum sleep time.

11. The integrated circuit of claim 10, wherein the power control circuit performs sleep time control by preventing a transition of the memory array between the sleep state and an operational state corresponding to one of the plurality of memory performance levels having a higher supply voltage if the counter indicates that the predetermined minimum sleep time has not yet elapsed.

12. The integrated circuit of claim 11, wherein the power control circuit is configurable to override the sleep time control to put the memory array in the operational state if a high priority access request is received.

13. The integrated circuit of claim 11, wherein the power status feedback unit further comprises a set of registers, and wherein the sleep time control depends upon a set of parameters stored in the registers and wherein at least a subset of the set of parameters is configurable.

14. The integrated circuit of claim 13, wherein the set of registers store at least one of:

a maximum count value indicating a predetermined minimum sleep time;

a power status value;

a power level threshold value;

a status ready value having one or more bits set when the counter reaches a maximum value and reset when the count is zero; and

a bypass value for specifying if the counter is currently bypassed.

15. The integrated circuit of claim 10, wherein the counter is configurable to switch between counting based on a bus/system clock and counting based on a low power clock.

16. A method of controlling access to a memory in an integrated circuit, the integrated circuit including a memory, a processor, and a power management controller having a voltage sensing circuit, the method comprising:

supplying the memory with a supply voltage corresponding to one of a plurality of memory performance levels including a full performance level and at least one power-saving performance level;

sensing a voltage level of a memory array of the memory with the voltage sensing circuit;

detecting, by the voltage sensing circuit, a voltage disturbance including a voltage dip of more than a predetermined minimum value, and using a counter to determine whether a duration of the voltage dip is greater than or equal to a threshold duration likely to result in data loss from memory;

generating a power status signal for the memory array indicating one of the plurality of memory performance levels of the memory depending upon the sensed voltage level and the duration of the voltage dip; and

permitting a memory access operation depending upon the value of the power status signal.

17. A controller for controlling access to a memory array of a memory circuit, comprising:

a voltage sensing circuit for receiving a sensed voltage level of the memory array;

a power management controller connected to the voltage sensing circuit for generating a power status signal indicating one of a plurality of memory performance levels of the memory circuit including a full performance level and at least one power-saving performance level, depending upon the sensed voltage level, and for permitting a memory access operation depending upon the value of the power status signal; and

a counter connected to the voltage sensing circuit, wherein if the voltage sensing circuit detects a voltage disturbance including a voltage dip of more than a predetermined minimum value, then the counter, upon detection of the voltage dip, performs a count to establish whether the duration of the dip is greater than or equal to a threshold duration likely to result in data loss from memory.