Multiple-precision processing block in a programmable integrated circuit device

• US 9,189,200 B1
• Filed: 03/14/2013
• Issued: 11/17/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/829,729
• Time in Patent Office: 978 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence

Abstract

A specialized processing block in a programmable integrated circuit device is configurable to perform floating-point arithmetic operations at selectable different precisions. The specialized processing block includes a plurality of different respective types of floating-point arithmetic operator structures. For each respective type of floating-point arithmetic operator structure, respective control circuitry for partitions the respective type of floating-point arithmetic operator structure to select between a first precision for which the respective type of floating-point arithmetic operator structure is not partitioned, and at least a second precision, less than the first precision, for which the respective type of floating-point arithmetic operator structure is partitioned into at least two smaller ones of the respective type of floating-point arithmetic operator structure.

Claims

1. A specialized processing block for performing floating-point arithmetic operations at selectable different precisions in a programmable integrated circuit device, said specialized processing block comprising:

a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure; and

for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure.

2. The specialized processing block of claim 1 wherein said plurality of different types of floating-point arithmetic operator circuit structures include at least one multiplier circuit structure and at least one adder circuit structure.

3. The specialized processing block of claim 2 wherein at least one of said at least one adder circuit structure includes shifting circuitry and rounding circuitry.

4. The specialized processing block of claim 3 wherein said rounding circuitry is selected from the group consisting of count-leading-zeroes circuitry, sticky bit circuitry, and combinations thereof.

5. The specialized processing block of claim 1 wherein said selectable different precisions comprise single precision and double precision.

6. The specialized processing block of claim 5 wherein said selectable different precisions further comprise single-extended precision.

7. The specialized processing block of claim 1 wherein said control circuitry for partitioning comprises circuitry for aligning portions of inputs into said respective type of floating-point arithmetic operator circuit structure to selected bits of said smaller ones of said respective type of floating-point arithmetic operator circuit structure.

8. The specialized processing block of claim 7 wherein said selected bits comprise least significant bits.

9. The specialized processing block of claim 7 wherein said selected bits comprise most significant bits.

10. The specialized processing block of claim 1 wherein:

each said respective type of floating-point arithmetic operator circuit structure includes at least two portions, each of said portions functioning as one of said smaller ones of said respective type of floating-point arithmetic operator circuit structure and having conductors connecting to at least one other one of said portions; and

said control circuitry for partitioning comprises a plurality of logic gates, each located on one of said conductors, for opening and closing said conductors;

wherein;

when said logic gates open said conductors, said respective type of floating-point arithmetic operator circuit structure is partitioned into said smaller ones of said respective type of floating-point arithmetic operator circuit structure; and

when said logic gates close said conductors,

said respective type of floating-point arithmetic operator circuit structure is not partitioned into said smaller ones of said respective type of floating-point arithmetic operator circuit structure.

11. The specialized processing block of claim 10 wherein said logic gates are AND-gates.

12. A method of configuring a programmable integrated circuit device to perform arithmetic operations at selectable different precisions, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising:

a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure, and

for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator circuit structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator circuit structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure, said method comprising;

configuring said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as a single block in which each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operates as a single one of said respective type of floating-point arithmetic operator circuit structure at said first precision, and operation of said specialized processing block as at least two sub-blocks, each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operating at said second precision as one of said respective type of floating-point arithmetic operator circuit structures in each of said sub-blocks.

13. The method of claim 12 wherein said plurality of different types of floating-point arithmetic operator circuit structures include at least one multiplier circuit structure and at least one adder circuit structure.

14. The method of claim 12 wherein at least one of said at least one adder circuit structure includes shifting circuitry and rounding circuitry.

15. The method of claim 14 wherein said rounding circuitry is selected from the group consisting of count-leading-zeroes circuitry, sticky bit circuitry, and combinations thereof.

16. The method of claim 12 wherein said configuring operation of said specialized processing block as a single block at said first precision comprises configuring said specialized block to operate at double precision.

17. The method of claim 16 wherein said configuring operation of said specialized processing block as at least two sub-blocks at said second precision comprises configuring said at least two sub-blocks to operate at one of selectable different precisions including single precision and single-extended precision.

18. The method of claim 12 wherein said configuring comprises:

partitioning said specialized processing block into at least two sub-blocks by partitioning each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures to operate as at least two of smaller ones of said respective type of floating-point arithmetic operator circuit structures; and

aligning portions of inputs into said respective type of floating-point arithmetic operator circuit structure to selected bits of said smaller ones of said respective type of floating-point arithmetic operator circuit structure.

19. The method of claim 18 wherein said selected bits comprise least significant bits.

20. The method of claim 18 wherein said selected bits comprise most significant bits.

21. The method of claim 12 wherein:

each said respective type of floating-point arithmetic operator circuit structure in said specialized processing block includes at least two portions, each of said portions functioning as one of said smaller ones of said respective type of floating-point arithmetic operator circuit structure and having conductors connecting to at least one other one of said portions, and said control circuitry for partitioning comprises a plurality of logic gates, each located on one of said conductors, for opening and closing said conductors; and

said configuring said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as said single block, and operation of said specialized processing block as at least two sub-blocks, comprises causing said logic gates to close said conductors for operation of said specialized processing block as said single block, and causing said logic gates to open said conductors for operation of said specialized processing block as said sub-blocks.

22. A non-transitory machine-readable storage medium encoded with instructions for performing a method of configuring a programmable integrated circuit device to perform arithmetic operations at selectable different precisions, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure, and for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator circuit structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator circuit structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure, said instructions comprising:

instructions to configure said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as a single block in which each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operates as a single one of said respective type of floating-point arithmetic operator circuit structure at said first precision, and operation of said specialized processing block as at least two sub-blocks, each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operating at said second precision as one of said respective type of floating-point arithmetic operator circuit structures in each of said sub-blocks.

23. The non-transitory machine-readable storage medium of claim 22 wherein said instructions comprise instructions selecting a plurality of different types of floating-point arithmetic operator circuit structures including at least one multiplier circuit structure and at least one adder circuit structure.

24. The non-transitory machine-readable storage medium of claim 23 wherein said instructions selecting a plurality of different types of floating-point arithmetic operator circuit structures including at least one multiplier circuit structure and at least one adder circuit structure comprise instructions to configure at least one of said at least one adder circuit structure to include shifting circuitry and rounding circuitry.

25. The non-transitory machine-readable storage medium of claim 23 wherein said instructions to configure at least one of said at least one adder circuit structure to include shifting circuitry and rounding circuitry comprise instructions selecting rounding circuits from the group consisting of count-leading-zeroes circuitry, sticky bit circuitry, and combinations thereof.

26. The non-transitory machine-readable storage medium of claim 22 wherein said instructions to configure operation of said specialized processing block as a single block at said first precision comprise instructions to configure said specialized block to operate at double precision.

27. The non-transitory machine-readable storage medium of claim 26 wherein said instructions to configure operation of said specialized processing block as at least two sub-blocks at said second precision comprise instructions to configure said at least two sub-blocks to operate at one of selectable different precisions including single precision and single-extended precision.

28. The non-transitory machine-readable storage medium of claim 22 wherein said instructions to configure comprise:

instructions to partition said specialized processing block into at least two sub-blocks by partitioning each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures to operate operating as at least two of smaller ones of said respective type of floating-point arithmetic operator circuit structures; and

instructions to align portions of inputs into said respective type of floating-point arithmetic operator circuit structure to selected bits of said smaller ones of said respective type of floating-point arithmetic operator circuit structure.

29. The non-transitory machine-readable storage medium of claim 28 wherein said selected bits comprise least significant bits.

30. The non-transitory machine-readable storage medium of claim 28 wherein said selected bits comprise most significant bits.

31. The non-transitory machine-readable storage medium of claim 22 wherein:

each said respective type of floating-point arithmetic operator circuit structure in said specialized processing block includes at least two portions, each of said portions functioning as one of said smaller ones of said respective type of floating-point arithmetic operator circuit structure and having conductors connecting to at least one other one of said portions, and said control circuitry for partitioning comprises a plurality of logic gates, each located on one of said conductors, for opening and closing said conductors; and

said instructions to configure said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as said single block, and operation of said specialized processing block as at least two sub-blocks, comprise instructions to cause said logic gates to close said conductors for operation of said specialized processing block as said single block, and instructions to cause said logic gates to open said conductors for operation of said specialized processing block as said sub-blocks.