Multiple-precision processing block in a programmable integrated circuit device
First Claim
1. A specialized processing block for performing floating-point arithmetic operations at selectable different precisions in a programmable integrated circuit device, said specialized processing block comprising:
- a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure; and
for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure.
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Abstract
A specialized processing block in a programmable integrated circuit device is configurable to perform floating-point arithmetic operations at selectable different precisions. The specialized processing block includes a plurality of different respective types of floating-point arithmetic operator structures. For each respective type of floating-point arithmetic operator structure, respective control circuitry for partitions the respective type of floating-point arithmetic operator structure to select between a first precision for which the respective type of floating-point arithmetic operator structure is not partitioned, and at least a second precision, less than the first precision, for which the respective type of floating-point arithmetic operator structure is partitioned into at least two smaller ones of the respective type of floating-point arithmetic operator structure.
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Citations
31 Claims
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1. A specialized processing block for performing floating-point arithmetic operations at selectable different precisions in a programmable integrated circuit device, said specialized processing block comprising:
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a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure; and for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of configuring a programmable integrated circuit device to perform arithmetic operations at selectable different precisions, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising:
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a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure, and for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator circuit structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator circuit structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure, said method comprising; configuring said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as a single block in which each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operates as a single one of said respective type of floating-point arithmetic operator circuit structure at said first precision, and operation of said specialized processing block as at least two sub-blocks, each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operating at said second precision as one of said respective type of floating-point arithmetic operator circuit structures in each of said sub-blocks. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A non-transitory machine-readable storage medium encoded with instructions for performing a method of configuring a programmable integrated circuit device to perform arithmetic operations at selectable different precisions, said programmable integrated circuit device including a specialized processing block, said specialized processing block comprising a plurality of different respective types of floating-point arithmetic operator circuit structures, each respective type of floating-point arithmetic operator circuit structure performing a different type of operation than each other type of floating-point arithmetic operator circuit structure, and for each respective type of floating-point arithmetic operator circuit structure, respective control circuitry within said floating-point arithmetic circuit structure for partitioning said respective type of floating-point arithmetic operator circuit structure to select between a first precision for which said respective type of floating-point arithmetic operator circuit structure is not partitioned, and at least a second precision, less than said first precision, for which said respective type of floating-point arithmetic operator circuit structure is partitioned into at least two smaller ones of said respective type of floating-point arithmetic operator circuit structure, said instructions comprising:
instructions to configure said respective control circuitry within said floating-point arithmetic circuit structure to select between operation of said specialized processing block as a single block in which each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operates as a single one of said respective type of floating-point arithmetic operator circuit structure at said first precision, and operation of said specialized processing block as at least two sub-blocks, each respective one of said plurality of different respective types of floating-point arithmetic operator circuit structures operating at said second precision as one of said respective type of floating-point arithmetic operator circuit structures in each of said sub-blocks. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
Specification