Generate random numbers using metastability resolution time
First Claim
1. A circuit for generation of a random output, the circuit comprising:
- a bistable circuit having two stable states as an output and a clock signal as an input, the bistable circuit comprising a first logic circuit and a second logic circuit cross-coupled connected together, the first and second logic circuits transitioning into a metastable state before resolving to the two stable states;
the second logic circuit resolves to a stable state at a resolution time; and
a digitization circuit configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal, the resolution time randomly varying according to noise;
wherein an actual value of the stable state is eliminated as a factor in generating the random bits.
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Accused Products
Abstract
A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.
18 Citations
20 Claims
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1. A circuit for generation of a random output, the circuit comprising:
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a bistable circuit having two stable states as an output and a clock signal as an input, the bistable circuit comprising a first logic circuit and a second logic circuit cross-coupled connected together, the first and second logic circuits transitioning into a metastable state before resolving to the two stable states; the second logic circuit resolves to a stable state at a resolution time; and a digitization circuit configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal, the resolution time randomly varying according to noise; wherein an actual value of the stable state is eliminated as a factor in generating the random bits. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for generation of a random output, the method comprising:
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generating a stable state after transitioning from a metastable state in a bistable circuit; detecting a resolution time to resolve from the metastable state to the stable state; and generating random bits corresponding to a variance of the resolution time resolving from the metastable state to the stable state for cycles of a clock signal, the resolution time randomly varying according to noise; wherein an actual value of the stable state is eliminated as a factor in generating the random bits. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer program product, tangibly embodied on a non-transitory computer readable medium, for generation of a random output, the computer program product including instructions that, when executed by a processor, cause the processor to perform operations comprising:
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generating a stable state after transitioning from a metastable state in a bistable circuit; detecting a resolution time to resolve from the metastable state to the stable state; and generating random bits corresponding to a variance of the resolution time resolving from the metastable state to the stable state for cycles of a clock signal, the resolution time randomly varying according to noise; wherein an actual value of the stable state is eliminated as a factor in generating the random bits. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification